• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Allegro X PCB Editor
  3. Allow overlapping soldermask

Stats

  • State Suggested Answer
  • Replies 11
  • Answers 1
  • Subscribers 163
  • Views 11383
  • Members are here 0
More Content

Allow overlapping soldermask

SOT23
SOT23 over 2 years ago

Hello,

I have some issues with the soldermask constraint set available in Constraint Manager > Analysis Mode.

At the moment, my constraints are set like this : 

And I have ticked the option Allow overlapping soldermask in Analysis Mode > Design for Fabrication.

Still, I have this kind of errors showing up : 

Info on the errors says : 

Class: DRC ERROR CLASS

  Subclass:        SOLDERMASK_TOP
  Origin xy:       (28.5588 37.5420)
  Constraint:      Symbol Soldermask to Pad Soldermask Spacing
  Constraint Set:  SOLDERMASK_SPACING
  Constraint Type: DESIGN
  Constraint value: 0.1 MM
  Actual value:     0 MM
  - - - - - - - - - - - - - - - - - - - -
  Element type:    SHAPE
  Class:           PACKAGE GEOMETRY
  Subclass:        SOLDERMASK_TOP
  RefDes:          MA8
  - - - - - - - - - - - - - - - - - - - -
  Element type:    VIA
  Class:           VIA CLASS
  origin-xy:    (28.4088 36.9420) 
  Part of net:       GND
  Connected pins:      1 ( TOP )
  Padstack name:   V65H30
  Usage:           Through_via  
  CIRCLE_DRILL  :  0.3000   Plated


The via is covered by 1:1 soldermask circle. As you can see, the soldermask shape from the symbol and the soldermask from the via are overlapping entirely. Still, Allegro throws an error for each via... Why is this happening ? As I understand it, the "Allow overlapping soldermask" should... Allow soldermask to overlap, right ? :p 

I don't want to remove the "Soldermask to pad and cline" DRC option because it allows me to spot places where soldermask could be uncovering a cline. But I want Allegro to allow soldermask that completly overlap. Is there a way to do that ?

Thank you in advance !!

PS : As a side note, the Info text from the "Allow overlapping soldermask" option is missing in the Analysis Mode box.

  • Sign in to reply
  • Cancel
  • avant
    0 avant over 2 years ago

    If the symbol has a soldermask shape, perhaps you can edit the vias and remove the soldermask. Edit the via, save as new name, replace.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • SOT23
    0 SOT23 over 2 years ago in reply to avant

    Hello, thank you for answering !

    I could do that, or I could just waive the DRC errors, but I would prefer to find a way to set the constrain right so that I don't have to work around what seems like a misconfiguration.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • steve
    0 steve over 2 years ago in reply to SOT23

    Try looking at setting the soldermask rules in Constraint Manager - Design for Fabrication settings. Currently there are two methods, one in Constraint Manager and one in Setup - Constraints - Modes. The overlap is only valid for the CM method. 

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • SOT23
    0 SOT23 over 2 years ago in reply to steve

    Hello Steve and thank you for answering.

    Are you talking about this option ? 

    If yes, it is ticked, but it doesn't seem to change anything. Should it remove these DRC ? To my understanding, it should, but maybe I am  wrong ?

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • steve
    0 steve over 2 years ago in reply to SOT23

    I don't think the DRC is going to do what you think it does. If you hover over the "i" at the end of the name you should see the info on what it does:-

    I don't believe there is a DRC check that will solve your issue so you can try and add a property to the PCB Footprint itself which would stop the DRC. Open the filename.dra then Edit - Properties, in the Find Pane click on the Find by Name dropdown and choose Drawing then look for nodrc_sym_shape_soldermask and nodrc_sym_pin_soldermask and add both those properties (Apply and OK). Then save the dra file. Then refresh this in the board and see if that resolves your issue.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
>
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information