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  3. Allow overlapping soldermask

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Allow overlapping soldermask

SOT23
SOT23 over 2 years ago

Hello,

I have some issues with the soldermask constraint set available in Constraint Manager > Analysis Mode.

At the moment, my constraints are set like this : 

And I have ticked the option Allow overlapping soldermask in Analysis Mode > Design for Fabrication.

Still, I have this kind of errors showing up : 

Info on the errors says : 

Class: DRC ERROR CLASS

  Subclass:        SOLDERMASK_TOP
  Origin xy:       (28.5588 37.5420)
  Constraint:      Symbol Soldermask to Pad Soldermask Spacing
  Constraint Set:  SOLDERMASK_SPACING
  Constraint Type: DESIGN
  Constraint value: 0.1 MM
  Actual value:     0 MM
  - - - - - - - - - - - - - - - - - - - -
  Element type:    SHAPE
  Class:           PACKAGE GEOMETRY
  Subclass:        SOLDERMASK_TOP
  RefDes:          MA8
  - - - - - - - - - - - - - - - - - - - -
  Element type:    VIA
  Class:           VIA CLASS
  origin-xy:    (28.4088 36.9420) 
  Part of net:       GND
  Connected pins:      1 ( TOP )
  Padstack name:   V65H30
  Usage:           Through_via  
  CIRCLE_DRILL  :  0.3000   Plated


The via is covered by 1:1 soldermask circle. As you can see, the soldermask shape from the symbol and the soldermask from the via are overlapping entirely. Still, Allegro throws an error for each via... Why is this happening ? As I understand it, the "Allow overlapping soldermask" should... Allow soldermask to overlap, right ? :p 

I don't want to remove the "Soldermask to pad and cline" DRC option because it allows me to spot places where soldermask could be uncovering a cline. But I want Allegro to allow soldermask that completly overlap. Is there a way to do that ?

Thank you in advance !!

PS : As a side note, the Info text from the "Allow overlapping soldermask" option is missing in the Analysis Mode box.

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  • SOT23
    0 SOT23 over 2 years ago in reply to steve

    I tried to see the info but there is no information for the "Allow overlapping solder mask" option. You can see it in my previous screenshot : it just displays DFF_OVERLAPPED_SOLDERMASK.

    I added both those properties to the symbol and updated the design (and the DRC), but the errors are still there

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  • steve
    0 steve over 2 years ago in reply to SOT23

    Difficult to debug screenshots but are are the shapes etc part of the filename.dra? If they are then you may need to send the board file to Cadence support or your channel partner (whoever you bought the software from) and see if they can look at in more detail.

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  • SOT23
    0 SOT23 over 2 years ago in reply to steve

    Hello,

    Yes, everything here (except traces and vias) are part of the .dra.

    Ok, I'll contact our channel partner. Thank you for the help !

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  • avant
    0 avant over 2 years ago in reply to SOT23

    Remove the soldermask from the vias (in the footprint) so you don't have an issue.

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  • jc teyssier
    0 jc teyssier over 2 years ago in reply to SOT23

    Try to add a shape on BOARD GEOMETRY/SOLDERMASK_TOP covering the faulty soldermask: normally DRC will not be here anymore.

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