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50MHz Clock Routing

melview1

I wanted a second opinion on how I'm routing a 50MHz Ethernet PHY clock trace.  4-layer PCB.  It is a trace that originates at the uP, goes to another uP pin (MAC) and then on to the PHY.  I have a series resistor at the origin and a 4 mil trace route, totaling about 1.3" after the resistor.  I have thru-routed the trace at the 2nd uP pin (in the back, out the front).  It remains on the Top layer and doesn't via.  I have removed most everything from near the trace.  The problem is that on this Top layer, there are 100 ohm differential traces that area setting the stackup dimensions.  H=8 mil between Top and Layer 2 (GND Plane).  These geometries make it difficult to achieve a 50 ohm 50MHz clock trace.  With W=4 mil and G=4 mil, a Coplanar Wave suggests it will be around 78 ohms.  Typically, I would target 50 ohms, but the uP pin drive impedance is 20 ohms, so maybe it's the wrong target?  I don't really want an 11.5 mil trace to achieve 50 ohms, but maybe I should consider it?  I'm not sure what my hang-up there is, it just seems odd to have a 10 mil clock trace.  The trace would be even larger if 20 ohms is the target.

My main concern is radiated EMI from the mismatched impedances and/or the routing of the trace.  Am I overthinking this and the length makes this all a moot point and/or I will be able to mitigate issues with adjusting the series resistor?  Or am I too far off on everything that EMI issues are more likely?  Does adding GND via stitching along the trace have any real benefit?  Any pros/cons and advice to this routing is appreciated.

Thanks,

Melview1

  • Hey Melview1 ... what's the dielectric constant of the material used for the PCB? 

  • in reply to JuanCR

    4.8
    I use the program Saturn PCB Toolkit to calculate impedances.

      

  • I would not be concerned in the slightest about 11.5mil trace width. I worked for many years with automotive pcb designs and, not too long ago, all traces were 0.3mm as standard for all copper traces including clock signals. Every single design had to be fully, independently tested for both noise immunity and emissions at test frequencies up to 1GHz as per the standard. So 0.3mm is not wide as such, it is just that standard traces have become narrow over the years. Narrowing traces is to help with design density; it is a challenge for EMI, not a benefit. So I would not be concerned about having 0.3mm wide traces and EMI issues. Increasing the trace width is really the cleanest and most effective way to adjust the impedance of this trace. Trying to adjust it with other methods could bring more problems to the table.

  • in reply to John T

    Thanks for the reply John.  I think I'm going to go ahead and change the line width.  I guess I don't have any Engineering reason not to do so.  On a related note, any thoughts on how the daisy chain from uP pin to uP pin then on to the source will affect the impedance?

  • in reply to melview1

    Hi Melview1. if you mean the characteristic impedance then it will not change however you connect, once the relationship to the reference plane underneath remains consistent. And you have opted for a stub-free connection, so I don't see any better way to connect than how you have done it. 

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