50MHz Clock Routing

I wanted a second opinion on how I'm routing a 50MHz Ethernet PHY clock trace.  4-layer PCB.  It is a trace that originates at the uP, goes to another uP pin (MAC) and then on to the PHY.  I have a series resistor at the origin and a 4 mil trace route, totaling about 1.3" after the resistor.  I have thru-routed the trace at the 2nd uP pin (in the back, out the front).  It remains on the Top layer and doesn't via.  I have removed most everything from near the trace.  The problem is that on this Top layer, there are 100 ohm differential traces that area setting the stackup dimensions.  H=8 mil between Top and Layer 2 (GND Plane).  These geometries make it difficult to achieve a 50 ohm 50MHz clock trace.  With W=4 mil and G=4 mil, a Coplanar Wave suggests it will be around 78 ohms.  Typically, I would target 50 ohms, but the uP pin drive impedance is 20 ohms, so maybe it's the wrong target?  I don't really want an 11.5 mil trace to achieve 50 ohms, but maybe I should consider it?  I'm not sure what my hang-up there is, it just seems odd to have a 10 mil clock trace.  The trace would be even larger if 20 ohms is the target.

My main concern is radiated EMI from the mismatched impedances and/or the routing of the trace.  Am I overthinking this and the length makes this all a moot point and/or I will be able to mitigate issues with adjusting the series resistor?  Or am I too far off on everything that EMI issues are more likely?  Does adding GND via stitching along the trace have any real benefit?  Any pros/cons and advice to this routing is appreciated.

Thanks,

Melview1