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  • For routing topologies, we use the PCB Designer (Professional) middle-tier license.

    I can set net schedules, pin pairs, min-max and relative delays. This is enough to define multi-chip Flash memory buss constraints.

    It's time consuming using the middle-tier license. I pretty much figured it out on my own, but I wonder if there are shortcuts or better methods than I am using.

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  • For routing topologies, we use the PCB Designer (Professional) middle-tier license.

    I can set net schedules, pin pairs, min-max and relative delays. This is enough to define multi-chip Flash memory buss constraints.

    It's time consuming using the middle-tier license. I pretty much figured it out on my own, but I wonder if there are shortcuts or better methods than I am using.

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