Cannot remove net from Relative Delay match group

Question

All differential pair nets in the design have been added to a Relative Delay match group. This has happened twice on this design. Allegro 17.2 S080 
 I cannot remove them. I get this error message: 
 
 INFO(SPCMGR-187): Cannot remove object "FLASH_B1_DQS_C" 
 from "FLASH_B0". 
 The object has flattened constraints from an Electrical CSet. 
 Deference the Electrical CSet to remove. 
 
 Anyone know what this message means?

avant · Answer

After wasting a lot of time on this, I concluded that the diff pairs are added to a match group when I assign the electrical constraint for phase tolerance. I defined the phase tolerance in the physical rules with no problem. 
 The diff pairs are defined on the schematic, and the "ignore electrical constraints" box was not checked when creating the netlist, so these come into the board as diff pairs. Unfortunately, this box is not checked by default, and I'm stuck with the netlist files I receive.

lfarg · Answer

I had the same issue, and I was able to resolve it by Unscheduling the nets in the layout: Logic > Net Schedule > Select Net > Unschedule Net > Finish. After the scheduling was removed, I was able to delete the extra pin pairs.

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Cannot remove net from Relative Delay match group

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