• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Allegro X PCB Editor
  3. via to via spacing on the same layer

Stats

  • State Verified Answer
  • Replies 7
  • Subscribers 159
  • Views 5143
  • Members are here 0
More Content

via to via spacing on the same layer

masamasa
masamasa over 1 year ago

hello

 

is there a way to check the via-to-via spacing on the same layer.

 

let us say we have 3 different padstacks, a, b, and c.

 

the constraint manager can allow the minimum sapcing setup between padstacks a and b but it seems there is no spacing setup between padstacks a and c

 

if the minimum spacing between padstacks a and b on different layers is set up, i can not catch the minimum spacing between padstacks a and c on the same layer.

 

all three vias have different nets.

 

regards

masa

  • Sign in to reply
  • Cancel
Parents
  • masamasa
    0 masamasa over 1 year ago

    thank u for ur response.

     

    the vias can be either with same nets and/or different nets.

     

    but most likely i would like to get a spacIng setup for different nets

     

    regards

    masa

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • Hoangkhoipcb
    0 Hoangkhoipcb over 1 year ago in reply to masamasa

    hi masamasa! Do you have any methods to handle that problem?

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • masamasa
    0 masamasa over 1 year ago in reply to Hoangkhoipcb

    no i do not.

     

    i do not have any method or solution to this problem so i posted this question.

     

    i hope cadence can give us a solution to this problem.

     

    regards

    masa

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
Reply
  • masamasa
    0 masamasa over 1 year ago in reply to Hoangkhoipcb

    no i do not.

     

    i do not have any method or solution to this problem so i posted this question.

     

    i hope cadence can give us a solution to this problem.

     

    regards

    masa

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
Children
  • Hoangkhoipcb
    +1 Hoangkhoipcb over 1 year ago in reply to masamasa

    i understand your issue. this is my method

    • Find minimun airgap via to via at the each layers( using cmd Min airgap).
    • Go to constraint manager adjust value as return before step.
    • Checking DRC error.

    I hope help you resolve  issue.

    Hoangkhoi

     

    • Cancel
    • Vote Up +1 Vote Down
    • Sign in to reply
    • Reject Answer
    • Cancel
  • masamasa
    0 masamasa over 1 year ago in reply to Hoangkhoipcb

    wow, thank u for ur response.

     

    yes this works.

     

    i did not know the setup for dielectric layers.

     

    regards

    masa

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
  • Hoangkhoipcb
    0 Hoangkhoipcb over 1 year ago in reply to masamasa

    you don't care dielectric layers. There is a example. Please change suitable your design.

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Verify Answer
    • Cancel
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information