via to via spacing on the same layer

-SPB 17.4 Hotfix 28 (QIR4) onward, you can set the same net checks for via pads and holes(Same net Hole to Hole and Via to Via checks) by using the Allegro PCB venture license.
-To set these checks, first, create the DFF CSet under Manufacturing > Design for Fabrication > DFF constraint set > Copper spacing and expand the 'Same net checks'.
-After creating DFF copper spacing CSet and setting the CSet usage as Etch, assign this CSet to the referenced DFF CSet under Design for Fabrication > Design > Copper Spacing.
-In analysis modes, enable the same net checks under Design For Fabrication > Copper Spacing.
Similarly, under Design for Fabrication>DFF constraint set>Copper Spacing, there are checks for 'Vias' here.
You might give it a try to see if it helps in your scenario to check via to via spacing.

thank u for ur response.

the vias can be either with same nets and/or different nets.

but most likely i would like to get a spacIng setup for different nets

regards

masa

hi masamasa! Do you have any methods to handle that problem?

no i do not.

i do not have any method or solution to this problem so i posted this question.

i hope cadence can give us a solution to this problem.

regards

masa

i understand your issue. this is my method

• Find minimun airgap via to via at the each layers( using cmd Min airgap).
• Go to constraint manager adjust value as return before step.
• Checking DRC error.

I hope help you resolve  issue.

Hoangkhoi