How to choose right stackup for your design?

This article guides you through planning a high-performance multilayer PCB stackup. The concept of the "perfect" stackup has evolved significantly, particularly with the advent of simulation tools that help us understand the intricate electrical behavior of transmission lines on PCBs.

Importance of stackup design: 

Planning the stackup configuration is crucial for achieving optimal product performance. A poorly designed stackup with inappropriate materials can lead to:

• Degraded signal transmission
• Increased emissions and crosstalk
• Susceptibility to external noise
• Intermittent operation and reduced reliability 

Benefits of a good stackup: 

A well-designed stackup offers several advantages:

• Reduced electromagnetic emissions and crosstalk
• Improved signal integrity
• Low-inductance power distribution network (PDN)
• Improved manufacturability and lower costs 

Optimizing the PDN: 

The PDN plays a vital role in high-speed designs. We want a low-inductance PDN to minimize high-frequency noise. The decoupling capacitors (Dcaps) provide instantaneous current to the drivers until the main power supply can respond. However, Dcaps have limitations due to their inherent inductance. Here's how to address this: 

• Multiple small-value Dcaps: Use several small-value Dcaps in parallel, placed close to power pins using thick, short traces. This reduces the overall series inductance.
• Interplane capacitance: Utilize the capacitance between power and ground planes for additional distributed capacitance across the board. However, Dcaps remain essential. 

Calculating interplane capacitance: 

Interplane capacitance (C) depends on the dielectric constant (Er) of the core material, the area of the plane (A), and the distance (d) between the planes: 

C = Er * A / d (where Er for FR4 is typically 4.3) 

Larger plane spacing results in lower capacitance. Aim for closer spacing (for example, 4 mil) for better high-frequency noise reduction. 

Reference planes and signal layers: 

Each signal layer needs a reference plane (ground or power) adjacent to it for a return current path. Ideally, limit embedded signal layers to one between planes and one on each outer layer. However, routing two signal layers between planes can create crosstalk unless they are orthogonal. 

Soldermask and impedance: 

Soldermask introduces a dielectric layer that slightly increases the trace's dielectric constant (Dk) compared to an unmasked trace. This can slow down signal propagation. The combined effect of soldermask thickness, Dk, and trace geometry determines the characteristic impedance (Zo) of the trace. For critical high-speed designs, consider the soldermask’s properties during impedance calculations. 

Determining layer count: 

The layer count depends on several factors: 

• Component technology: Smaller components require tighter tolerances, leading to more layers.
• Characteristic impedance (Zo) and differential impedance (Zdiff): These are determined by component datasheets and influence the number of layers needed.
• Design complexity: More signal nets, power supplies, and components necessitate more layers.

Estimating layer requirements: 

• Technology rules: Define minimum trace widths, clearances, and via sizes based on the chosen component technology.
• Impedance calculations: Calculate the required stackup for desired Zo and Zdiff.
• Auto-routing: Use an auto-router to test routability. Aim for at least 85% completion with minimal tweaking to indicate a sufficient layer count.

Conclusion: 

Careful stackup planning is essential for high-speed PCB design. By understanding the factors discussed here, you can create a stackup that optimizes electrical performance, manufacturability, and cost.

Additional considerations: 

• The specific effects of soldermask and other materials will depend on their properties and the overall stackup configuration.
• Consult datasheets for accurate Dk and thickness values of materials used in your design.

An ideal stackup should be like the stackup shown in the screenshot below: