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  3. About Allegro max stacked via count in DFF rule

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About Allegro max stacked via count in DFF rule

zpofrp
zpofrp 11 months ago

There are many bbvia or uvia in my design, Via_L1_L4,Via_L2_L3,Via_L5_L6,Via_L1_L2, and so on. The Via_L5_L6 is PTH via. orther via is laser via.

I want to check the max laser via count and laser via count in PTH via.

I find a fuction in manufacturing> design for fabrication. But it's not what I wanted.

For example i set the max stacked via count =2, But there is no DRC when Via L1 to L6(Via_L1_L5+ Via_L5_L6).

Only bbvia count nore than 2, Via_L1_L2+ Via_L2_L3+Via_L3_L4.

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  • John T
    John T 11 months ago

    Hi zpofrp, so you are stating that the uvia is not counted, only the bbvias - is that correct? You mention that "Via_L5_L6" is a PTH so I am little confused by this...

    Can you tell us if the uvias are defined in the bbvia definitions? It is possible to mark these as uvia in this interface: 

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  • zpofrp
    zpofrp 11 months ago in reply to John T

    There are laser via and mechanical via in the package deign. The PTH is Plating Through Hole, usually it  through the Core layer.

    I don't defined the uvias in the bb via definitions. I have never used Uvia. I will relize Uvia.

    I want to show the DRC for max via count more than 3. for example L1 to L4, L2 to L5,L3 to L6, and so on.

    I mean the max via count is the number that passes through the dielectric.

    But the DFF is set based on bbvia or Uvia count.

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  • zpofrp
    zpofrp 11 months ago in reply to John T

    There are laser via and mechanical via in the package deign. The PTH is Plating Through Hole, usually it  through the Core layer.

    I don't defined the uvias in the bb via definitions. I have never used Uvia. I will relize Uvia.

    I want to show the DRC for max via count more than 3. for example L1 to L4, L2 to L5,L3 to L6, and so on.

    I mean the max via count is the number that passes through the dielectric.

    But the DFF is set based on bbvia or Uvia count.

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