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Net-tie without manually specifying net names

pertinax

I want to create a net-tie in the schematic and layout. I.e., a schematic symbol with two pins and a corresponding footprint with two shorted pins.  See the screenshots below.

I have read this document https://www.parallel-systems.co.uk/wp-content/uploads/2020/02/Netshort_Definition.pdf and also this RAK https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V000007MqM1UAK&pageName=ArticleContent.

Without adding any properties, the shorted footprint causes DRC errors in the layout. In my case I get "SMD Pin to Pin Spacing" DRC. It is possible to add a NET_SHORT property, either to the schematic component as described in the first document or in the layout using the "net short" command. However, this requires either specifying the exact net names in the schematic property or manually performing the net short in the layout.

In the second document above, I read about the PIN_SHORT property. Apparently it can be added to the schematic symbol, giving the names of the pins, and the "packager" will automatically create the NET_SHORT property during packaging. I added the property PIN_SHORT=1:2 to the schematic symbol, with pin names for the pins set to "1" and "2". This did not work.

I read that the packager needs the option "PROCESS_PIN_SHORT_PROP 'ON'" for this to work (page 12 of the RAK). However, I don't know if this is applicable to Orcad X Professional (PCB Editor 23.1), or where to add this said option. According to the document, it needs to be added to the "project cpm file" or "site cpm file".

Thanks for any help!

  • 0

    I generally use a zero-ohm resistor to tie two nets together.

    You can create a footprint with two pins and a drawn line between the pins.

    Put the drawn line onto a non-etch layer and remember to add this layer to your artwork layer.

    DRC won't flag this as an error, but I'd add a note that this short is intentional on the fab drawing. The fab shop will flag it during a net check.

  • 0

    To create a net-tie without manually specifying net names in OrCAD PCB Editor, ensure the following:

    1. Add the property PIN_SHORT=1:2 to the schematic symbol with correct pin names.
    2. Verify that the packager option PROCESS_PIN_SHORT_PROP 'ON' is enabled.
    3. Locate the CPM file under your project directory or site settings and edit it to include this option.
    4. If issues persist, double-check pin assignments and packaging rules in the schematic.
    5. Consult Cadence support if the option isn't recognized in version 23.1.
  • +1

    Hi there.

    There is another way to do this. In the schematic you cab use any 2 pin symbol you like. In the PCB Symbol Editor create a 2 pin symbol where by both pins are shorted together so as to form a jumper. A good method to do this is to use "Shape Pins"  because they can  made so as to overlap each other. In the Symbol editor the overlapped pins will create a visible DRC. This is normal.

    Before saving the symbol add this property to the symbol. Nodrc_Sym_Same_Pin.

    In the PCB editor the symbol wont have a drc because of the property added to the symbol. When you package PCB from the schematic and using this symbol the net result will be 2 shorted nets on the board.

    Best regards.

  • 0 in reply to excellon1

    Hi and thanks! This seems like a good method. I  tried to add the Nodrc_Sym_Same_Pin property to the symbol, but didn't find a way. There is the "Setup/Property definitions..." dialog, but it won't let me add this property since it is reserved. And I cannot add a property with the standard "Edit/Properties" without selecting an object.

  • +1 in reply to pertinax

    Hi, In the symbol editor adding properties works differently, try the following.

    On the tool bar click on Edit menu and choose "Properties"

    Next go to the find filter. On the find filter panel there will be a drop down selection - Find by name. Usually this shows symbol. Click that drop down button and choose "Drawing". This will open up the edit properties panel where you can add properties to the symbol. You should see
    Nodrc_Sym_Same_Pin in the list which will allow you to add it to the symbol.

    When creating the symbol, I think making the pins a shape symbol works best as opposed to using regular padstacks. For example you could create a pad that tapers out so as to form what looks like a trace for each pad. When you add the shape pins it's just a matter of sliding the pins so they overlap slightly. Drc will show up.

    I use this method based on a 1206 footprint. Basically replicate the pad as a shape with outward taper. I tried to post a picture but seems like cadence board is DOA from here.

    Give that a try and see if it works for you.

    Best regards.

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