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Allegro 17.4 PCB Designer Trying to create a netlist report with Part Number and Alias.

NP202510093218

Howdy all,

I'm using Cadence Allegro 17.4. I made a schematic capture with signal names. However when i do a netlist report i get a name that is not the signal name, I get the origin name of the net. I tried in Allegro Design Authoring: Design Entry HDL and Allegro PCB Designer 17.4.

That makes sense that intermediate signals are not listed, however I'm trying to check that I have the pin out labeled correctly according to an Excel doc. 

Is there anyway to generate a report with these signal?

Ideally Id like a report like PR1 | 5_B10 | GND_S_S8, not the MB01_006052.... identifier.

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  • excellon1
    0

    Hi,

    I use orcad capture front end here and it can put out what you are after. The format is

    <<< Wire List >>>

    NODE  REFERENCE    PIN #   PIN NAME           PIN TYPE       PART VALUE

    [00001] CLOCK
            U1                               11          CLK                     Passive            ADF4110

    Node Reference would be the Net Name like 5_B1 in your picture.

    Not sure if this helps but to access it in orcad go to tools > Create Netlist. Choose the Other Tab and select orWirelist.dll. There is also a check box to tick. Sort Nets by net names and view output.

    You could probably pull this into excel and remove the columns you don't need, maybe do some reformatting too.

    I am not too sure what GND_S_S8 is ?

    Best Regards.

  • JCTEYSSIER0
    0 in reply to excellon1

    What i guess:

    - PR1 is pin name

    - 5_B10 is pin number

    - GND_S_S8  is signal name

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