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Is there any check available in Allegro to catch the impedance traces running parallel on adjacent layers?

BC202603263145

Hi,

I have a 6-layer stackup with differential pairs routed on L4 and L5. Since the board density is high, I want to avoid having these traces run parallel to each other across these layers.

Is there a check available in Allegro to detect such parallel routing violations?

Thanks!

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  • JuanCR
    0

    I think what you want you can achieve with the DRC MAX_PARALLEL. You find it in Constraint Manager > Electrical Constraints > Routing > Wiring > Max Parallel


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  • JuanCR
    0

    I think what you want you can achieve with the DRC MAX_PARALLEL. You find it in Constraint Manager > Electrical Constraints > Routing > Wiring > Max Parallel


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