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  3. What is Preventing Designers from Improving Decoupling?

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What is Preventing Designers from Improving Decoupling?

John T
John T 28 days ago

We see many designs every day but most do not follow the performance recommendations when it comes to power and ground via placement for decoupling capacitors.

Why ?

What is preventing you from pushing your designs to perform at their electrical best:
1. Is it costs?
2. Is it due to manufacturing or fabrication?
3. Is it speed for design completion or DRC management?

The highest level recommendation is to place grounding and power vias inside the capacitor pads

Let’s share some industry experience if anyone has overcome these hurdles or have suggestions or reasons for the approach.

Appreciating any thoughts or comments below.

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  • avant
    avant 18 days ago +2
    We don't use via-in-pad. We produce 1M+ units a year. Expense and manufacturing issues outweigh benefit for us. We typically use #2 with vias tied to planes, and wide traces. We use a lot of 0201…
  • excellon1
    excellon1 21 days ago +1
    Hi John, Good topic. The caps look too big for the pads :), probably just to illustrate I'm sure. So Level 3 works very well, I have used this fairly regularly as I do RF based layouts into the GHz.…
  • avant
    avant 17 days ago in reply to John T +1
    Hi John, I should have clarified - Our designs are usually single-sided with only optional memory and related components on the back side. Decoupling caps for the top side components are on the top…
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  • avant
    avant 18 days ago

    We don't use via-in-pad. 

    We produce 1M+ units a year.

    Expense and manufacturing issues outweigh benefit for us.

    We typically use #2 with vias tied to planes, and wide traces.

    We use a lot of 0201 decoupling caps.

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  • John T
    John T 17 days ago in reply to avant

    Hi Avant, yes this rings a bell with me too having previously designed for high volume production also. 

    Does anyone ever pre-plan placement to account for smd side1 versus smd side2 assembly? One neat trick we came up with was placing vias in pad for components placed on the smd 2 side. Side 1 being already pasted and soldered; any paste that might come through due to the side 2 soldering will then not cause any interference with production of the opposite side, such as no stencil lifting. 

    Would be interested to hear any other thoughts or tricks!

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  • avant
    avant 17 days ago in reply to John T

    Hi John,

    I should have clarified - Our designs are usually single-sided with only optional memory and related components on the back side.

    Decoupling caps for the top side components are on the top side. Placement is not ideal.

    Interesting idea about vias on smd 2 side.

    Best Regards

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  • John T
    John T 10 days ago in reply to avant

    Sometimes it makes you wonder if it would be possible to embed just the ground pad on the lower layer, soldering directly to the inner ground plane...For thin dielectric layers the thickness difference might not be so bad to enable soldering potentially. The technology is already there for making punch openings in the prepreg, or just micro-milling. Hope my meaning is clear.  

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  • John T
    John T 10 days ago in reply to avant

    Sometimes it makes you wonder if it would be possible to embed just the ground pad on the lower layer, soldering directly to the inner ground plane...For thin dielectric layers the thickness difference might not be so bad to enable soldering potentially. The technology is already there for making punch openings in the prepreg, or just micro-milling. Hope my meaning is clear.  

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