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What is Preventing Designers from Improving Decoupling?

John T

We see many designs every day but most do not follow the performance recommendations when it comes to power and ground via placement for decoupling capacitors.

Why ?

What is preventing you from pushing your designs to perform at their electrical best:
1. Is it costs?
2. Is it due to manufacturing or fabrication?
3. Is it speed for design completion or DRC management?

The highest level recommendation is to place grounding and power vias inside the capacitor pads

Let’s share some industry experience if anyone has overcome these hurdles or have suggestions or reasons for the approach.

Appreciating any thoughts or comments below.

  • in reply to avant

    Sometimes it makes you wonder if it would be possible to embed just the ground pad on the lower layer, soldering directly to the inner ground plane...For thin dielectric layers the thickness difference might not be so bad to enable soldering potentially. The technology is already there for making punch openings in the prepreg, or just micro-milling. Hope my meaning is clear.  

  • in reply to excellon1

    Thanks for the detailed explanation. I’m still fairly new to PCB layout, so some of this is new to me, but the point about keeping the trace width closer to the pin width makes sense. I’ll keep the via placement and inductance in mind as well.

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