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  3. ERROR(SPMHNI-175) IN CREATING THE NETLIST

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ERROR(SPMHNI-175) IN CREATING THE NETLIST

AnirudhTHABJUL
AnirudhTHABJUL over 9 years ago

Hello Everyone,

I am electronic engineer working in Paris.

I am using ORCAD 16.6 for designing our schematics and PCB layout.

In order to design the PCB layout we need to create NETLIST file right.

So, while creating this netlist i have got following error

" ERROR: File "SNB_PSB.brd" is being edited by user "THABJUL" on date "Mon Nov 30 15:20:05 2015" on system "ANIRUDH_THABJUL". Resolve lock file and re-run netrev.

#1 ERROR(SPMHNI-175): Netrev error detected."

Can any body help me in solving this issue?

Regards,
Anirudh

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  • steve
    0 steve over 9 years ago
    Setup - Design Parameters - Design tab and change the long name size from 31 to 255. You can set this by default from Setup - User Preferences - drawing and set the value there for allegro_long_name_size.
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  • steve
    0 steve over 9 years ago
    Setup - Design Parameters - Design tab and change the long name size from 31 to 255. You can set this by default from Setup - User Preferences - drawing and set the value there for allegro_long_name_size.
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  • KONAKONDLA
    0 KONAKONDLA over 5 years ago in reply to steve

    #1 ERROR(SPMHNI-175): Netrev error detected.

    #2 Run stopped because errors were detected

    netrev run on Nov 14 11:40:59 2019
    DESIGN NAME : 'NRF52832_BLU_A01A'
    PACKAGING ON Mar 2 2016 00:37:24

    COMPILE 'logic'
    CHECK_PIN_NAMES OFF
    CROSS_REFERENCE OFF
    FEEDBACK OFF
    INCREMENTAL OFF
    INTERFACE_TYPE PHYSICAL
    MAX_ERRORS 500
    MERGE_MINIMUM 5
    NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'
    NET_NAME_LENGTH 24
    OVERSIGHTS ON
    REPLACE_CHECK OFF
    SINGLE_NODE_NETS ON
    SPLIT_MINIMUM 0
    SUPPRESS 20
    WARNINGS ON

    2 errors detected
    No oversight detected
    No warning detected

    cpu time 0:00:15
    elapsed time 0:00:00

    INFO(ORCAP-32005): *** Done ***

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  • steve
    0 steve over 5 years ago in reply to KONAKONDLA

    Check the Session log for the actual errors. Post that up if you are unsure

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  • TECHNIQUES
    0 TECHNIQUES over 4 years ago in reply to steve

    Checking Entire Design: Trial_1
    --------------------------------------------------

    INFO(ORCAP-2212): Check Power Ground Mismatch
    QUESTION(ORCAP-1589): Net has two or more aliases - possible short? VD3P3_SI
    QUESTION(ORCAP-1589): Net has two or more aliases - possible short? VCC_ETH_1V1
    QUESTION(ORCAP-1589): Net has two or more aliases - possible short? V5P0
    QUESTION(ORCAP-1589): Net has two or more aliases - possible short? VCC_3V3
    QUESTION(ORCAP-1589): Net has two or more aliases - possible short? VD3P3
    QUESTION(ORCAP-1589): Net has two or more aliases - possible short? VCCINT_C5
    QUESTION(ORCAP-1589): Net has two or more aliases - possible short? GND
    QUESTION(ORCAP-1589): Net has two or more aliases - possible short? VIO1_FX
    QUESTION(ORCAP-1589): Net has two or more aliases - possible short? VD1P8

    Reporting Unused Refdes in multiple part packages
    Part Quantity Reference
    -----------------------------------------------------------------------------------------

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