Stats

  • Locked Locked
  • Replies 7
  • Subscribers 163
  • Views 17436
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

High speed DDR multi-tiered T routing

archive

Hey all,

I'm trying to setup some matched length T routing for some high speed DDR memory. I have scheduled the nets properly with virtual pins and setup pin pairs in constraint manager under Relative Propagation Delay but I don't understand how to specify a length range for the individual pin pairs of the T route. Should this be setup somewhere besides Relative Prop Delay?

Image 1: multi-tiered T routing of DDR address buss. All segments A must match length. All segments B & C must match length. All segments D, E, F and G must match length. Data buss length must match address segment length to each DDR.

I'm running 15.5.1 with the performance option.

Any help would be appreciated....need to get moving on this board!!!!!

Parents
  • archive

    Just newby here.. Great Explanation. I Just had some few questions, bout your pdf, not all DDR wiring is the same as the specs as explained.. correct me if i'm wrong. For example, Some ddr wiring doesn't have any pair DQS wiring as mentioned in your document. In this case, should i wire the DQS together with the byte lane? example: DQ<7...0>and DQS1, DQ<15..0>andDQS2..etc.
    Every Design has a different specification.. Most of the design i made, mostly customers wants ALL data and Addresses of the same length together. How could it be? Anyway I'm just two years in PCB design profession that's why need some clarities especially when it comes to sensitive part of design such as DDR and CPUs. Thanks.

Reply
  • archive

    Just newby here.. Great Explanation. I Just had some few questions, bout your pdf, not all DDR wiring is the same as the specs as explained.. correct me if i'm wrong. For example, Some ddr wiring doesn't have any pair DQS wiring as mentioned in your document. In this case, should i wire the DQS together with the byte lane? example: DQ<7...0>and DQS1, DQ<15..0>andDQS2..etc.
    Every Design has a different specification.. Most of the design i made, mostly customers wants ALL data and Addresses of the same length together. How could it be? Anyway I'm just two years in PCB design profession that's why need some clarities especially when it comes to sensitive part of design such as DDR and CPUs. Thanks.

Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.