High speed DDR multi-tiered T routing

Hi,
Relative propagation delay is the corect place for this constraint to live.

There are acoupel of ways of getting the constraint into the field. The easiest to visualise is through sigexplorer.

Open constraint manager, find a representitve net, right click it and open sig xp for that net.

It's probably worth spending a few minutes at this point cleaning up the canvas, so that the tlines and receivers are layed out as per your diagram above.

Now use the menu and open "constraints" Move to the relative propagation delay.

Here you must create a pin pair and matched group name for each of the lengths that you wish to constrain.

I looks like you are laying out data, so may I suggest:

("MGx" = matched group name)

"MG1" pin pair defining D, scope local.
"MG1" pin pair defining E, scope local.
"MG1" pin pair defining F, scope local.
"MG1" pin pair defining G, scope local.

These will match D, E, F & G within each net.

Then:
"MG2" pin pair defining A+B+D, scope global (or bus).
Which will match the length of D + E within this net, either to all nets upon which you apply this ECSet (global) or to all nets within the current bus (bus scope.) This is the matched group that is used to tie the 8 data bits together with the strobe in a DDR bus.

Once the constraints are all set up, save the topology from sigxp and import it into constraint manager as an ECSet. Then apply the EC Set to your databus.

If you don't have Sigxp, you can do the same thing from constraint manager, but it's a little less visual. open a generic data bus net, and right click then create > pin pair to make the required pin pairs. Next fill in the constraints and scopes in the relative propagation box. Finally you create an ECSet from the gerneic net and apply as before.


Can I point you at:
http://www.cdnusers.org/community/allegro/Resources/kits_designin/memory/stp_cdnliveemea07_ddrconstraints_veal.pdf
It's a presentation I wrote for CdnLive last year on DDR constraints, it might be useful to you.

Hope that helps.

Just newby here.. Great Explanation. I Just had some few questions, bout your pdf, not all DDR wiring is the same as the specs as explained.. correct me if i'm wrong. For example, Some ddr wiring doesn't have any pair DQS wiring as mentioned in your document. In this case, should i wire the DQS together with the byte lane? example: DQ<7...0>and DQS1, DQ<15..0>andDQS2..etc.
Every Design has a different specification.. Most of the design i made, mostly customers wants ALL data and Addresses of the same length together. How could it be? Anyway I'm just two years in PCB design profession that's why need some clarities especially when it comes to sensitive part of design such as DDR and CPUs. Thanks.

DQS actually starts life as a single ended signal. During bringup of the DDR interface the controller turns on differential DQS in the DRAM.

DQS needs to be the target of thematched group for each data byte, regardless of whether it's a single ended or differential signal.

It is not necessary to route the ADDR bus the same length to every chip. Doing so will quickly get your design all tangled up. Check the DRAM spec for clock to Address tolerance and then clock to data. You should find clock to addr is reasonably tight, but clock to data (strobe) is loose.

So, make sure clock and ADDR arrive simultaneously at each DRAM. Don't worry about any skew between DRAM devices. Each DRAM has no knowledge of the 8 other DRAMS in the rank, so why does the address have to arrive at all drams simultaneously?

Make sure each data byte is closely matched to it's strobe.

Finally, make sure that the strobes are loosely aligned to the clock.

If your customer is asking you to match Address to data, address (DRAM1) to address (DRAM 2) then I'm not sure they understand DDR.

Dear Vealmic,

in your presentation you remark not to talk about detailed timing equations etc. We want to route a 12bit 500Mbit DDR2 bus with DStrobe and want to calculate what tolerances we can allow for the data and bus lenght matching. Can you give us a hint how or where I can find information about to calculate the timings, to set the correct propagation delay values?

Thanks a lot!

Hello Hermann,
The following is a generic approach that can be applied to any bus.

Start with a transaction going in one direction on the bus.

Start with the transmitter of the transaction.
Take the INTERNAL ASIC clock signal as a reference for that transaction.
Now look at each signal in turn and find the skew relative to the internal clock signal (note that the external clock signal will also have a skew relative to the internal clock). The skew will probably be expressed as two figures giving you the earliest and latest signals.

Next you need to formulate an equation for each line on the bus.
You need to know about the skew relative to that signals timing reference.
For example D0 references DQS0
If DQS can vary +/- 100ps (I'm making these values up, they bear no resemblance to real life) relative to the internal ASIC clock, amd
D0 can vary +/-300ps relative to the internal ASIC Clock then

D0 can vary +/- 400ps relative to DQS.

Next, you go to the datasheet for the receiver of the transaction.
Look up the required relaitonship for D0 to DQS. You may find that you have +/-1ns. So, you know that the maximum skew allowed by the net is 1ns - 400ps =(+/-) 600ps.

You now have a static timing equation. But only for data travelling in one direction. If data can flow the other way, you need to swap the direction of data flow and repeat the process. You will then have two equations. Lets say that one direction say the nets can have +/-600ps and the other gives you +400 / -700. Your constraint will become:
D0 = DQS +400/-600 ps.

You do need to take into account any noise injected into the net that will make the signal slower to settle. The noise could be reflections or crosstalk, or even groundbounce. So your static equation is a start, but does not emcompass everything you need to know.

Please don't ask me to give further detail than this! Mainly becasue I'd be guessing at the answers, I'm a logic designer, whilst I speak a bit of SI and know a bit about high speed techniques, I am not a SI engineer.

Hope that helps you.