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High speed DDR multi-tiered T routing

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Hey all,

I'm trying to setup some matched length T routing for some high speed DDR memory. I have scheduled the nets properly with virtual pins and setup pin pairs in constraint manager under Relative Propagation Delay but I don't understand how to specify a length range for the individual pin pairs of the T route. Should this be setup somewhere besides Relative Prop Delay?

Image 1: multi-tiered T routing of DDR address buss. All segments A must match length. All segments B & C must match length. All segments D, E, F and G must match length. Data buss length must match address segment length to each DDR.

I'm running 15.5.1 with the performance option.

Any help would be appreciated....need to get moving on this board!!!!!

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    Dear Vealmic,

    in your presentation you remark not to talk about detailed timing equations etc. We want to route a 12bit 500Mbit DDR2 bus with DStrobe and want to calculate what tolerances we can allow for the data and bus lenght matching. Can you give us a hint how or where I can find information about to calculate the timings, to set the correct propagation delay values?

    Thanks a lot!

Reply
  • archive

    Dear Vealmic,

    in your presentation you remark not to talk about detailed timing equations etc. We want to route a 12bit 500Mbit DDR2 bus with DStrobe and want to calculate what tolerances we can allow for the data and bus lenght matching. Can you give us a hint how or where I can find information about to calculate the timings, to set the correct propagation delay values?

    Thanks a lot!

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