High speed DDR multi-tiered T routing

Hello Hermann,
The following is a generic approach that can be applied to any bus.

Start with a transaction going in one direction on the bus.

Start with the transmitter of the transaction.
Take the INTERNAL ASIC clock signal as a reference for that transaction.
Now look at each signal in turn and find the skew relative to the internal clock signal (note that the external clock signal will also have a skew relative to the internal clock). The skew will probably be expressed as two figures giving you the earliest and latest signals.

Next you need to formulate an equation for each line on the bus.
You need to know about the skew relative to that signals timing reference.
For example D0 references DQS0
If DQS can vary +/- 100ps (I'm making these values up, they bear no resemblance to real life) relative to the internal ASIC clock, amd
D0 can vary +/-300ps relative to the internal ASIC Clock then

D0 can vary +/- 400ps relative to DQS.

Next, you go to the datasheet for the receiver of the transaction.
Look up the required relaitonship for D0 to DQS. You may find that you have +/-1ns. So, you know that the maximum skew allowed by the net is 1ns - 400ps =(+/-) 600ps.

You now have a static timing equation. But only for data travelling in one direction. If data can flow the other way, you need to swap the direction of data flow and repeat the process. You will then have two equations. Lets say that one direction say the nets can have +/-600ps and the other gives you +400 / -700. Your constraint will become:
D0 = DQS +400/-600 ps.

You do need to take into account any noise injected into the net that will make the signal slower to settle. The noise could be reflections or crosstalk, or even groundbounce. So your static equation is a start, but does not emcompass everything you need to know.

Please don't ask me to give further detail than this! Mainly becasue I'd be guessing at the answers, I'm a logic designer, whilst I speak a bit of SI and know a bit about high speed techniques, I am not a SI engineer.

Hope that helps you.

Hello Hermann,
The following is a generic approach that can be applied to any bus.

Start with a transaction going in one direction on the bus.

Start with the transmitter of the transaction.
Take the INTERNAL ASIC clock signal as a reference for that transaction.
Now look at each signal in turn and find the skew relative to the internal clock signal (note that the external clock signal will also have a skew relative to the internal clock). The skew will probably be expressed as two figures giving you the earliest and latest signals.

Next you need to formulate an equation for each line on the bus.
You need to know about the skew relative to that signals timing reference.
For example D0 references DQS0
If DQS can vary +/- 100ps (I'm making these values up, they bear no resemblance to real life) relative to the internal ASIC clock, amd
D0 can vary +/-300ps relative to the internal ASIC Clock then

D0 can vary +/- 400ps relative to DQS.

Next, you go to the datasheet for the receiver of the transaction.
Look up the required relaitonship for D0 to DQS. You may find that you have +/-1ns. So, you know that the maximum skew allowed by the net is 1ns - 400ps =(+/-) 600ps.

You now have a static timing equation. But only for data travelling in one direction. If data can flow the other way, you need to swap the direction of data flow and repeat the process. You will then have two equations. Lets say that one direction say the nets can have +/-600ps and the other gives you +400 / -700. Your constraint will become:
D0 = DQS +400/-600 ps.

You do need to take into account any noise injected into the net that will make the signal slower to settle. The noise could be reflections or crosstalk, or even groundbounce. So your static equation is a start, but does not emcompass everything you need to know.

Please don't ask me to give further detail than this! Mainly becasue I'd be guessing at the answers, I'm a logic designer, whilst I speak a bit of SI and know a bit about high speed techniques, I am not a SI engineer.

Hope that helps you.