Stats

  • Locked Locked
  • Replies 7
  • Subscribers 163
  • Views 17436
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

High speed DDR multi-tiered T routing

archive

Hey all,

I'm trying to setup some matched length T routing for some high speed DDR memory. I have scheduled the nets properly with virtual pins and setup pin pairs in constraint manager under Relative Propagation Delay but I don't understand how to specify a length range for the individual pin pairs of the T route. Should this be setup somewhere besides Relative Prop Delay?

Image 1: multi-tiered T routing of DDR address buss. All segments A must match length. All segments B & C must match length. All segments D, E, F and G must match length. Data buss length must match address segment length to each DDR.

I'm running 15.5.1 with the performance option.

Any help would be appreciated....need to get moving on this board!!!!!

Parents
  • archive

    Hmmn, That wasn't a very good answer.
    DO will be issued from your ASIC before DQS.
    It needs to arrive at the DDR before DQS (setup time) and remain stable for a period after DQS (hold time).
    The static equations need to incluse the setup and hold times.
    Generally your ASIC will generate enough setup and hold for you, but there may be instances where the requirements of one end of the bus are different to the other.
    Err, so please add setup and hold to the static equations.

Reply
  • archive

    Hmmn, That wasn't a very good answer.
    DO will be issued from your ASIC before DQS.
    It needs to arrive at the DDR before DQS (setup time) and remain stable for a period after DQS (hold time).
    The static equations need to incluse the setup and hold times.
    Generally your ASIC will generate enough setup and hold for you, but there may be instances where the requirements of one end of the bus are different to the other.
    Err, so please add setup and hold to the static equations.

Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.