• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design
  3. Illegal section pin value - Design Entry CIS

Stats

  • Locked Locked
  • Replies 2
  • Subscribers 165
  • Views 1269
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Illegal section pin value - Design Entry CIS

sigit
sigit over 16 years ago

Dear all,

When I tried to generate netlist for (Allegro) PCB Editor
v16.0, I had this messages :

Loading... E:\.........\ SKEMATIK\ NETLIST_VER1_ REPLACED_ COMP/pstxnet. dat
packaging the design view...Illegal section pin value
Illegal section pin value
Illegal section pin value
Illegal section pin value
......

Does anyone know what it means? is it an error or just warnings?

FYI, the netlist is successfully generated and I can do import netlist in Allegro PCB Editor,  but I'm still curious about the messages

many thanks,

sigit

  • Cancel
  • oldmouldy
    oldmouldy over 16 years ago

    Just a guess but hard to tell anything without seeing the source design.

    Check that you have the latest service release, for 16.0, that was issued at the end of March and can be downloaded from the downloads site with a Sourcelink account, or download and install 16.01 and it's latest service release, if the DE CIS version is .p001, that will be a base release and may be the problem.

    Something else to try is the "other" netlist tab, select the "wirelist.dll" for a simple text netlist, this may flag the issue. Generally, it would be unusual for the PCB Editor netlist to be generated if there were any issues with the data. Since the error looks to be from the pstxnet checking, the issue could be a pin number or inconsistent pin properties, not too easy to create with the tool.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • sigit
    sigit over 16 years ago

     Yes,my DE CIS version is .p001. I've tried to generate netlist by selecting the "wirelist.dll", and it seems okay. All I have is just this messages :

    Netlist Format: wirelist.dll
    Design Name: E:\.......\SKEMATIK\BOARD_VS_VER1_FINAL.DSN
    774 Parts, 54 Library Parts, 786 Nets, 3743 Pins
    Initialize
    WARNING: Name is too long 'DIFFIO_R30p/DQS1R', truncated to DIFFIO_R30p/DQS
    WARNING: Name is too long 'DIFFIO_R16n(x/x/IO)', truncated to DIFFIO_R16n(x/x
    WARNING: Name is too long 'DIFFIO_R26n(NC/NC/x)', truncated to DIFFIO_R26n(NC/
    .....

    DONE

     

    I'll try the latest service release for 16.0 and find out the outcome. Thanks a lot.

     

     

     

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information