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Illegal section pin value - Design Entry CIS

sigit

Dear all,

When I tried to generate netlist for (Allegro) PCB Editor v16.0, I had this messages :

Loading... E:\.........\ SKEMATIK\ NETLIST_VER1_ REPLACED_ COMP/pstxnet. dat
packaging the design view...Illegal section pin value
Illegal section pin value
Illegal section pin value
Illegal section pin value
......

Does anyone know what it means? is it an error or just warnings?

FYI, the netlist is successfully generated and I can do import netlist in Allegro PCB Editor,  but I'm still curious about the messages

many thanks,

sigit

Parents
  • sigit

     Yes,my DE CIS version is .p001. I've tried to generate netlist by selecting the "wirelist.dll", and it seems okay. All I have is just this messages :

    Netlist Format: wirelist.dll
    Design Name: E:\.......\SKEMATIK\BOARD_VS_VER1_FINAL.DSN
    774 Parts, 54 Library Parts, 786 Nets, 3743 Pins
    Initialize
    WARNING: Name is too long 'DIFFIO_R30p/DQS1R', truncated to DIFFIO_R30p/DQS
    WARNING: Name is too long 'DIFFIO_R16n(x/x/IO)', truncated to DIFFIO_R16n(x/x
    WARNING: Name is too long 'DIFFIO_R26n(NC/NC/x)', truncated to DIFFIO_R26n(NC/
    .....

    DONE

     

    I'll try the latest service release for 16.0 and find out the outcome. Thanks a lot.

     

     

     

Reply
  • sigit

     Yes,my DE CIS version is .p001. I've tried to generate netlist by selecting the "wirelist.dll", and it seems okay. All I have is just this messages :

    Netlist Format: wirelist.dll
    Design Name: E:\.......\SKEMATIK\BOARD_VS_VER1_FINAL.DSN
    774 Parts, 54 Library Parts, 786 Nets, 3743 Pins
    Initialize
    WARNING: Name is too long 'DIFFIO_R30p/DQS1R', truncated to DIFFIO_R30p/DQS
    WARNING: Name is too long 'DIFFIO_R16n(x/x/IO)', truncated to DIFFIO_R16n(x/x
    WARNING: Name is too long 'DIFFIO_R26n(NC/NC/x)', truncated to DIFFIO_R26n(NC/
    .....

    DONE

     

    I'll try the latest service release for 16.0 and find out the outcome. Thanks a lot.

     

     

     

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