• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design
  3. Unused Pad deletion

Stats

  • Locked Locked
  • Replies 5
  • Subscribers 166
  • Views 14200
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Unused Pad deletion

Wild
Wild over 16 years ago

 Is there a way to deleted unused pads on a given layer other than during gerber generation? 

I have a dual row 50 pin connector and am routing high voltage routes through pins and am getting DRC's.  I'd like to verfy that when the pad is removed that I am not voilating my net spacing constraint.

 

  • Cancel
Parents
  • Wild
    Wild over 16 years ago

     We are using 15.7 :)

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Wild
    Wild over 16 years ago

     We are using 15.7 :)

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information