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Can I 'fix' a constraint to a footprint once it's placed?

EvanShultz

I have an 8-pin header for a footprint that has 3 leads for each logical connection (pin in the header). The schematic symbol only shows one pin for each logical connection, and the footprint uses the pin and a pair of vias. The annular rings of the vias are touching and there is a Cline connecting the pins and each via on the Top and Bottom copper layers. When the footprint is placed on the board, "Thru Via to Thru Via Same Net Spacing" DRC errors are created because the vias are overlapping. See the attached picture.

I can eliminate the DRC errors by changing the SNS constraints in CM (I am using 16.2). But I'd rather assign some property/constraint on the footprint, so I don't have to mess with CM for this one circumstance. If I set a constraint in CM on the DRA file, that constraint is overridden by the board's constraints once the footprint is placed. Is there a way to set a property/constraint on the footprint that will 'stick' even once the footprint is placed on a board with differing SNS contraints?

  • Rik Lee

    Try adding the property NODRC_SYM_SAME_PIN

    NODRC_SYM_SAME_PIN
    The NODRC_SYM_SAME_PIN property, attached to a board, symbol instance, or symbol definition, disables pin-to-pin conductive layer checking between pins of the same symbol. Pin-to-pin checking always occurs in a symbol editor (.dra). Pin-to-pin spacing checks between different symbols remain unaffected. 

     

    Edit >Properties

    In the "Find" tab set the pulldobnw to "Drawing" and select "More"

    In the "Find by Name or Property" GUI push "Drawing Select" over to the right and select "Apply"

    In the "Edit Property" GUI move NODRC_SYM_SAME_PIN to the right, apply the change and then OK out of all fors.

     

    ~Rik

  • EvanShultz

     Hi Rik,

     Thanks for the suggestion! Unfortunately, the DRC error is being created between vias that touch on the symbol, not pins. So this property won't help me.

    Any other ideas?

  • EvanShultz

     Hi all,

     The solution, in my case, was to put the NO_DRC property on one of the vias. This cleared up the DRC errors but of course requires manual checking for violations. One could always remove this propety right before fabrication to verify there are no other DRC errors.

  • aCraig

    Evan,

     Why not waive the DRC(s) instead of completely masking them with NO_DRC. If you waive it you shouldn't have to do any other manual checks since the VIA can still create other DRCs.

     Craig

  • jch teyssier

     Be aware that "NO_DRC" property is dangerous:

    if you (or whatever person working on the design) add a trace thru tis via (and why not, a second trace on the vi on other layer...), then you would obtain a shortcircuit. 

    Use this property ONLY if you KNOW what can be the consequences.

     

    Jean-Charles 

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