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Orcad Layout DRC issue

BTM73

I have an issue where a padstack was not defined for inner layers for a particular pin and caused a short to the two plane layers. This was not caught by Layout's DRC but was fortunately caught by the PCB vendor. Any help in resolving this would be greatly appreciated.

Thanks!

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  • redwire

     Check your error/warnings during artwork output -- bet it showed up there.  Allegro will let you produce gerbers with warnings. :(

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  • redwire

     Check your error/warnings during artwork output -- bet it showed up there.  Allegro will let you produce gerbers with warnings. :(

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