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Length matching multi-device serial bus with chip selects

pcbeng25

I am trying to write routing rules for Allegro PCB Router v16.3 to match trace lengths for a serial bus (clk/data) with a chip select for each device on the chain.  The source FPGA devA needs to deliver a clock, data, and CS to each of 4 devices on the chain.  The clk and data lines go from devA -> dest1 -> dest2 -> dest3 -> dest4.  There are 4 chip selects which go directly from devA to each of the destinations.  Each CS line has to be length matched with the clk and data line segments from devA to its particular destination.  I have tried to make groups and group sets along with the match_group_length command, but it seems to match all the CS lines to the total routed length of the clock and data lines instead of the segments leading up to the destination.

 define (group uclk0 (fromto devA dest1))
define (group udat0 (fromto devA dest1))
define (group ucs0 (fromto devA dest1))
define (group_set uwire0 uclk0 udat0 ucs0)
circuit group_set uwire0 (match_group_length on (tolerance 0.05))
rule group_set uwire0 (patterns_allowed accordian)
rule group_set uwire0 (limit_way 7)

define (group uclk1 (fromto devA dest1) (fromto dest1 dest2))
define (group udat1 (fromto devA dest1) (fromto dest1 dest2))
define (group ucs1 (fromto devA dest2)))
define (group_set uwire1 uclk1 udat1 ucs1)
circuit group_set uwire1 (match_group_length on (tolerance 0.05))
rule group_set uwire1 (patterns_allowed accordian)
rule group_set uwire1 (limit_way 7)

 define (group uclk2 (fromto devA dest1) (fromto dest1 dest2) (fromto dest2 dest3))
define (group udat2 (fromto devA dest1) (fromto dest1 dest2) (fromto dest2 dest3))
define (group ucs2 (fromto devA dest3))
define (group_set uwire2 uclk2 udat2 ucs2)
circuit group_set uwire2 (match_group_length on (tolerance 0.05))
rule group_set uwire2 (patterns_allowed accordian)
rule group_set uwire2 (limit_way 7)

define (group uclk3 (fromto devA dest1) (fromto dest1 dest2) (fromto dest2 dest3) (fromto dest3 dest4))
define (group udat3 (fromto devA dest1) (fromto dest1 dest2) (fromto dest2 dest3) (fromto dest3 dest4))
define (group ucs3 (fromto devA dest4)))
define (group_set uwire3 uclk3 udat3 ucs3)
circuit group_set uwire3 (match_group_length on (tolerance 0.05))
rule group_set uwire3 (patterns_allowed accordian)
rule group_set uwire3 (limit_way 7)

 

These rules conflict though apparently because fromtos are shared between them.  Is there a way of doing this and achieving the desired result?

 

Parents
  • lcanx2
    One way to solve this problem is to create 4 match groups in the Constraint Manager.

    Each match group would have 2 pin pairs defining the FPGA to destination pin, one for the clock net and one for the data net.

    Each match group would also have its corresponding Chip select network (or you could create, and then include a pin pair for Chip Select).

    Then I would send that over to the PCB Router with all your other rules defined in your do file.

    Bill

    I am trying to write routing rules for Allegro PCB Router v16.3 to match trace lengths for a serial bus (clk/data) with a chip select for each device on the chain.  The source FPGA devA needs to deliver a clock, data, and CS to each of 4 devices on the chain.  The clk and data lines go from devA -> dest1 -> dest2 -> dest3 -> dest4.  There are 4 chip selects which go directly from devA to each of the destinations.  Each CS line has to be length matched with the clk and data line segments from devA to its particular destination.  I have tried to make groups and group sets along with the match_group_length command, but it seems to match all the CS lines to the total routed length of the clock and data lines instead of the segments leading up to the destination.

     
Reply
  • lcanx2
    One way to solve this problem is to create 4 match groups in the Constraint Manager.

    Each match group would have 2 pin pairs defining the FPGA to destination pin, one for the clock net and one for the data net.

    Each match group would also have its corresponding Chip select network (or you could create, and then include a pin pair for Chip Select).

    Then I would send that over to the PCB Router with all your other rules defined in your do file.

    Bill

    I am trying to write routing rules for Allegro PCB Router v16.3 to match trace lengths for a serial bus (clk/data) with a chip select for each device on the chain.  The source FPGA devA needs to deliver a clock, data, and CS to each of 4 devices on the chain.  The clk and data lines go from devA -> dest1 -> dest2 -> dest3 -> dest4.  There are 4 chip selects which go directly from devA to each of the destinations.  Each CS line has to be length matched with the clk and data line segments from devA to its particular destination.  I have tried to make groups and group sets along with the match_group_length command, but it seems to match all the CS lines to the total routed length of the clock and data lines instead of the segments leading up to the destination.

     
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