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Length matching multi-device serial bus with chip selects

pcbeng25

I am trying to write routing rules for Allegro PCB Router v16.3 to match trace lengths for a serial bus (clk/data) with a chip select for each device on the chain.  The source FPGA devA needs to deliver a clock, data, and CS to each of 4 devices on the chain.  The clk and data lines go from devA -> dest1 -> dest2 -> dest3 -> dest4.  There are 4 chip selects which go directly from devA to each of the destinations.  Each CS line has to be length matched with the clk and data line segments from devA to its particular destination.  I have tried to make groups and group sets along with the match_group_length command, but it seems to match all the CS lines to the total routed length of the clock and data lines instead of the segments leading up to the destination.

 define (group uclk0 (fromto devA dest1))
define (group udat0 (fromto devA dest1))
define (group ucs0 (fromto devA dest1))
define (group_set uwire0 uclk0 udat0 ucs0)
circuit group_set uwire0 (match_group_length on (tolerance 0.05))
rule group_set uwire0 (patterns_allowed accordian)
rule group_set uwire0 (limit_way 7)

define (group uclk1 (fromto devA dest1) (fromto dest1 dest2))
define (group udat1 (fromto devA dest1) (fromto dest1 dest2))
define (group ucs1 (fromto devA dest2)))
define (group_set uwire1 uclk1 udat1 ucs1)
circuit group_set uwire1 (match_group_length on (tolerance 0.05))
rule group_set uwire1 (patterns_allowed accordian)
rule group_set uwire1 (limit_way 7)

 define (group uclk2 (fromto devA dest1) (fromto dest1 dest2) (fromto dest2 dest3))
define (group udat2 (fromto devA dest1) (fromto dest1 dest2) (fromto dest2 dest3))
define (group ucs2 (fromto devA dest3))
define (group_set uwire2 uclk2 udat2 ucs2)
circuit group_set uwire2 (match_group_length on (tolerance 0.05))
rule group_set uwire2 (patterns_allowed accordian)
rule group_set uwire2 (limit_way 7)

define (group uclk3 (fromto devA dest1) (fromto dest1 dest2) (fromto dest2 dest3) (fromto dest3 dest4))
define (group udat3 (fromto devA dest1) (fromto dest1 dest2) (fromto dest2 dest3) (fromto dest3 dest4))
define (group ucs3 (fromto devA dest4)))
define (group_set uwire3 uclk3 udat3 ucs3)
circuit group_set uwire3 (match_group_length on (tolerance 0.05))
rule group_set uwire3 (patterns_allowed accordian)
rule group_set uwire3 (limit_way 7)

 

These rules conflict though apparently because fromtos are shared between them.  Is there a way of doing this and achieving the desired result?

 

  • lcanx2
    One way to solve this problem is to create 4 match groups in the Constraint Manager.

    Each match group would have 2 pin pairs defining the FPGA to destination pin, one for the clock net and one for the data net.

    Each match group would also have its corresponding Chip select network (or you could create, and then include a pin pair for Chip Select).

    Then I would send that over to the PCB Router with all your other rules defined in your do file.

    Bill

    I am trying to write routing rules for Allegro PCB Router v16.3 to match trace lengths for a serial bus (clk/data) with a chip select for each device on the chain.  The source FPGA devA needs to deliver a clock, data, and CS to each of 4 devices on the chain.  The clk and data lines go from devA -> dest1 -> dest2 -> dest3 -> dest4.  There are 4 chip selects which go directly from devA to each of the destinations.  Each CS line has to be length matched with the clk and data line segments from devA to its particular destination.  I have tried to make groups and group sets along with the match_group_length command, but it seems to match all the CS lines to the total routed length of the clock and data lines instead of the segments leading up to the destination.

     
  • lcanx2

    When I define the match group settings you describe in the Constraint Manager of PCB Editor and send it over to the PCB Router I get the following format:

    define (group _REL_DELAY_FPGA_DEST1

    (fromto DEVA-C0 DEST1-14 (type soft))

    (fromto DEVA-D0 DEST1-21 (type soft))

    (fromto DEVA-CS0 DEST1-22 (type soft))

    )

    define (group _REL_DELAY_FPGA_DEST2

    (fromto DEVA-C1 DEST2-15 (type soft))

    (fromto DEVA-D1 DEST2-24 (type soft))

    (fromto DEVA-CS1 DEST2-52 (type soft))

    )

    define (group _REL_DELAY_FPGA_DEST3

    (fromto DEVA-C2 DEST3-17 (type soft))

    (fromto DEVA-D2 DEST3-28 (type soft))

    (fromto DEVA-CS2 DEST3-29 (type soft))

    )

    define (group _REL_DELAY_FPGA_DEST4

    (fromto DEVA-C3 DEST4-31 (type soft))

    (fromto DEVA-D3 DEST4-44 (type soft))

    (fromto DEVA-CS3 DEST4-20 (type soft))

    )

     

    Bill

  • pcbeng25

    I'm not sure I understand that result.  That seems to define 4 groups...which is fine.  However how do I get them to match properly.  The clock and data lines chain from one device to another.  DEVA is the source of C0, D0, CS0, CS1, CS2, and CS3.  C1 comes from C0, C2 from C1, and C3 from C2...same for the data lines.

     I want to match the following:

    C0 to D0, C1 to D1, C2 to D2 and C3 to D3

    Then, the chip selects to the length of the clock and data lines to the desired destination.

    CS0 to C0

    CS1 to C0+C1

    CS2 to C0+C1+C2

    CS3 to C0+C1+C2+C3

    where all the C segments were also matched to their respective D segments.  This will basically time align the chip select with the clock and data.  This is important in this design, becuase when the slave device detects a falling edge on the chip select, it reads data starting on the next rising edge...i.e. the master started sending data on the rising edge of the clock line immediately following setting the chip select line low.  I was hoping there was a way for the router to take care of this with my DO file rules instead of me having to go in later and manually adjust all the trace lengths.

    If that is what your post does, can you explain a bit further for me?

     Thanks for your reply.

  • lcanx2

    Right, and if I understand your required topology, which I believe I do, I think this will get you close. My earlier example was innacurate as it did not refer back to the source pins for the clock and data on DEVA for each relative delay group, that is key. I tried this example in the router and brought it back to Allegro and although the router failed the length by a couple hundred mils it achieves the individual data/clock segment matching as well as matches fairly well the chip select length to the accumulated lengths of each clock/data destination point. I do hope this gets you over the hurdle if you have not done so already yourself.

    Bill

    define (group _REL_DELAY_U91_MG

    (fromto U120-11 U91-12 (type soft))

    (fromto U120-10 U91-11 (type soft))

    (fromto U91-7 U120-7 )

    )

    define (group _REL_DELAY_U96_MG

    (fromto U120-11 U96-12 (type soft))

    (fromto U120-10 U96-11 (type soft))

    (fromto U96-6 U120-6 )

    )

    define (group _REL_DELAY_U102_MG

    (fromto U120-11 U102-12 (type soft))

    (fromto U120-10 U102-11 (type soft))

    (fromto U102-5 U120-13 )

    )

    define (group _REL_DELAY_U113_MG

    (fromto U120-11 U113-12 (type soft))

    (fromto U120-10 U113-11 (type soft))

    (fromto U113-13 U120-12 )

    )

    define (group QLM0_MUX_CLK_IN_N

    (fromto U16-14 R33-1 )

    (fromto R431-1 R33-2 )

    (fromto U9-3 R431-1 )

  • pcbeng25

    Bill.  Thanks for the reply...I just got this, the email was stuck in our SPAM quarantine.  I thank you for your help.  This has gotten me close enough to be within our tolerances.

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