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Packaging Error

IanByrne over 14 years ago

When I try to package my schematic design for layout, I get errors, not able to create file.

I have a .brd file created already but can't import the logic.

Help?

Parents

IanByrne over 14 years ago

This is the errorlog I get when I run the packager but DO NOT try to update the PCB Editor:

    Cadence Design Systems, Inc.
    Packager-XL 16.2-p002 (v16-2-57B) WIN32 10/7/2008 12:00:00 IST
    (C) Copyright 1994, Cadence Design Systems, Inc.

    Run on Tue Mar 15 11:25:43 2011

**********************************************
* Processing project file and command line *
**********************************************

    ANNOTATE 'BODY' 'PIN'
    COMP_DEF_PROP 'ALT_SYMBOLS' 'ALT_SYMBOLS_HARD' 'JEDEC_TYPE' 'MERGE_NC_PINS'
                   'MERGE_POWER_PINS' 'MOUNT_SIDE' 'NC_PINS' 'PART_NUMBER'
                   'PINCOUNT' 'POWER_GROUP' 'POWER_PINS'
    COMP_INST_PROP 'DEFAULT_SIGNAL_MODEL' 'GROUP' 'PART_NUMBER' 'REUSE_ID'
                    'REUSE_INSTANCE' 'REUSE_NAME' 'ROOM' 'SIGNAL_MODEL'
                    'SYMBOL_EDITED' 'VOLT_TEMP_SIGNAL_MODEL' 'ISRFELEMENT'
                    'RFELEMENTTYPE' 'RFLAYER' 'RFLAYER1' 'RFLAYER2' 'RFLAYER3'
                    'RFLAYER4' 'RFLAYER5' 'RFLAYER6' 'RFLAYER7' 'RFLAYER8'
                    'RFLAYER9' 'RFLAYER10' 'RFLAYER11' 'RFLAYER12' 'RFLAYER13'
                    'RFLAYER14' 'RFLAYER15' 'RFLAYER16' 'RFCOUPLINGMODE'
                    'RFFLIPMODE' 'RFANGLE' 'RFANGLE1' 'RFWIDTH' 'RFWIDTH1'
                    'RFWIDTH2' 'RFWIDTH3' 'RFWIDTH4' 'RFWIDTH5' 'RFWIDTH6'
                    'RFWIDTH7' 'RFWIDTH8' 'RFWIDTH9' 'RFWIDTH10' 'RFWIDTH11'
                    'RFWIDTH12' 'RFWIDTH13' 'RFWIDTH14' 'RFWIDTH15' 'RFWIDTH16'
                    'RFLENGTH' 'RFLENGTH1' 'RFLENGTH2' 'RFLENGTH3' 'RFLENGTH4'
                    'RFLENGTH5' 'RFLENGTH6' 'RFLENGTH7' 'RFLENGTH8' 'RFSPACING'
                    'RFSPACING1' 'RFSPACING2' 'RFSPACING3' 'RFSPACING4'
                    'RFSPACING5' 'RFSPACING6' 'RFSPACING7' 'RFSPACING8'
                    'RFSPACING9' 'RFSPACING10' 'RFSPACING11' 'RFSPACING12'
                    'RFSPACING13' 'RFSPACING14' 'RFSPACING15' 'RFOFFSETX'
                    'RFOFFSETY' 'RFRADIUS' 'RFDEPTH' 'RFFREQUENCY'
                    'RFMITERFRACTION' 'RFBENDMODE' 'RFNUMBERLEGS'
                    'RFNUMBERPAIRS' 'RFNUMBERTURNS' 'RFCAPACITANCE'
                    'RFRESISTANCE' 'RFINDUCTANCE' 'RFPADSTACKNAME'
                    'RFPADSSMNAME1' 'RFPADSSMNAME2' 'RFPADBEGINLAYER'
                    'RFPADENDLAYER' 'RFPADLINEWIDTH1' 'RFPADLINEWIDTH2'
                    'RFPADDIAMETER1' 'RFPADDIAMETER2' 'RFPADLENGTH1'
                    'RFPADLENGTH2' 'RFHOLEDIAMETER' 'RFPADANGLE' 'RFDRANAME'
                    'RFPADTYPE' 'RFUID' 'RFBLOCK' 'RFDCNET'
    SUPPRESS_GLOBAL_SHORT_CHECK OFF
    DEBUG    0
    DEFAULT_PHYS_DES_PREFIX U
    FEEDBACK 'OFF'
    INCLUDE_PPT u:/cadence_libs/released/part_table
    MAX_ERRORS 999
    NET_NAME_CHARS   @ - ! # % & ( ) * . / : ? [ ] ^ _ ` +
                     = > 0 1 2 3 4 5 6 7 8 9
    NET_NAME_LENGTH 31
    NUM_OLD_VERSIONS 3
    OPTIMIZE OFF
    REUSE_REFDES ON
    OPF_OPTIMIZATION OFF
    HARD_LOC_SEC OFF
    FORCE_PTF_ENTRY OFF
    REGENERATE_PHYSICAL_NET_NAME OFF
    SCH_POWER_GROUP_WINS_OVER_PPT OFF
    NULL_OPT_VALID OFF
    USE_VECTOR_NOTATION ON
    FILTER_ECS_FROM_XNET ON
    OUTPUT 'ON'
    PACKAGE_PROP 'GROUP' 'ROOM'
    PART_TYPE_LENGTH 128
    PPT u:/cadence_libs/released/part_table
    REF_DES_LENGTH 31
    REPACKAGE ON
    ELECTRICAL_CONSTRAINTS ON
    OVERWRITE_CONSTRAINTS ON
    RUN_DIR ./worklib/design_ce_eu_power_board/packaged/
    STRICT_PACKAGE_PROP 'REUSE_INSTANCE'
    USE_LIBRARY_PPT ON
    USE_STATE OFF
    WARNINGS ON
    LIBRARY 'ce_eu_power_board_lib' 'standard' 'ant' 'battery' 'capacitor_bp'
             'capacitor_pol' 'coil_inductor' 'connector' 'diode' 'diode_zener'
             'display_lcd' 'display_led' 'ferrite_bead' 'filter' 'fuse' 'ic'
             'jumper_wire' 'misc' 'radio' 'res' 'res_network' 'sensor' 'switch'
             'thermistor' 'transformer' 'transistor' 'unreleased' 'varistor'
             'vreg' 'xtal_osc'
    CDSPROP_FILE
    VIEW_PTF part_table
    VIEW_PACKAGER packaged
    VIEW_CONSTRAINTS constraints
    DESIGN_LIBRARY ce_eu_power_board_lib
    DESIGN_NAME design_ce_eu_power_board
    VIEW_CONFIG_PHYSICAL cfg_package
    SD_SUFFIX_SEPARATOR _
    STOP_PST_GEN_ON_PTF_MISMATCH ON
    IGNORE_PRIM_BINDING OFF
    LOG_INST_PHYS_PATH ON
    ANNOTATE_VISIBLE_SEC OFF
    PTF_MISMATCH_EXCLUDE_INJ_PROP 'ALL'
    IMPORT_HFS_HARDSEC_ON_SWAP_PINS OFF
    ALLOW_PTFVALUE_INITIAL_BLANKS ON
    PRESERVE_UNSUBSTITUTED_MACROS OFF
    CACHE_ENABLED OFF
    CACHE_NAME cache
    PTF_NAME cache

**************************************************************
* End processing project file and command line (00:00:00) *
**************************************************************

Creating Configuration "cfg_package" for Design "design_ce_eu_power_board"

Processing Constraints File ./worklib/design_ce_eu_power_board/constraints/des~
ign_ce_eu_power_board.dcf.
INFO(SPCODD-181): Loading c:\cadence\SPB_16.2\share\cdssetup\cdsprop.tmf.
INFO(SPCODD-181): Loading c:\cadence\SPB_16.2\share\cdssetup\cdsprop.paf.
#1   WARNING(SPCODD-360): PPT file "u:/cadence_libs/released/part_table" not ~
found in any of the directories specified by the PPT directive.

*********************************
* Loading the design database *
*********************************

#1   ERROR(SPCODD-103): Could not find logical part '1A' for primitive instan~
ce '@CE_EU_POWER_BOARD_LIB.DESIGN_CE_EU_POWER_BOARD(SCH_1):PAGE1_I8@DIODE.DIO_~
SCHOTTKY(CHIPS)'.
Check 'PART_NAME' property in chips_prt file.
INFO(SPCOPK-1441): 1 errors detected
INFO(SPCOPK-1443): 1 warnings detected
INFO(SPCOPK-1448): Use Tools->Markers->Packager in ConceptHDL to highlight ins~
tances for the errors/warnings reported.
    Start time   11:25:43
    End time     11:25:47
    Elapsed time 0:00:04

**************************************************
* FATAL ERROR PackagerXL exiting with status 2 *
**************************************************
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IanByrne over 14 years ago

This is the errorlog I get when I run the packager but DO NOT try to update the PCB Editor:

    Cadence Design Systems, Inc.
    Packager-XL 16.2-p002 (v16-2-57B) WIN32 10/7/2008 12:00:00 IST
    (C) Copyright 1994, Cadence Design Systems, Inc.

    Run on Tue Mar 15 11:25:43 2011

**********************************************
* Processing project file and command line *
**********************************************

    ANNOTATE 'BODY' 'PIN'
    COMP_DEF_PROP 'ALT_SYMBOLS' 'ALT_SYMBOLS_HARD' 'JEDEC_TYPE' 'MERGE_NC_PINS'
                   'MERGE_POWER_PINS' 'MOUNT_SIDE' 'NC_PINS' 'PART_NUMBER'
                   'PINCOUNT' 'POWER_GROUP' 'POWER_PINS'
    COMP_INST_PROP 'DEFAULT_SIGNAL_MODEL' 'GROUP' 'PART_NUMBER' 'REUSE_ID'
                    'REUSE_INSTANCE' 'REUSE_NAME' 'ROOM' 'SIGNAL_MODEL'
                    'SYMBOL_EDITED' 'VOLT_TEMP_SIGNAL_MODEL' 'ISRFELEMENT'
                    'RFELEMENTTYPE' 'RFLAYER' 'RFLAYER1' 'RFLAYER2' 'RFLAYER3'
                    'RFLAYER4' 'RFLAYER5' 'RFLAYER6' 'RFLAYER7' 'RFLAYER8'
                    'RFLAYER9' 'RFLAYER10' 'RFLAYER11' 'RFLAYER12' 'RFLAYER13'
                    'RFLAYER14' 'RFLAYER15' 'RFLAYER16' 'RFCOUPLINGMODE'
                    'RFFLIPMODE' 'RFANGLE' 'RFANGLE1' 'RFWIDTH' 'RFWIDTH1'
                    'RFWIDTH2' 'RFWIDTH3' 'RFWIDTH4' 'RFWIDTH5' 'RFWIDTH6'
                    'RFWIDTH7' 'RFWIDTH8' 'RFWIDTH9' 'RFWIDTH10' 'RFWIDTH11'
                    'RFWIDTH12' 'RFWIDTH13' 'RFWIDTH14' 'RFWIDTH15' 'RFWIDTH16'
                    'RFLENGTH' 'RFLENGTH1' 'RFLENGTH2' 'RFLENGTH3' 'RFLENGTH4'
                    'RFLENGTH5' 'RFLENGTH6' 'RFLENGTH7' 'RFLENGTH8' 'RFSPACING'
                    'RFSPACING1' 'RFSPACING2' 'RFSPACING3' 'RFSPACING4'
                    'RFSPACING5' 'RFSPACING6' 'RFSPACING7' 'RFSPACING8'
                    'RFSPACING9' 'RFSPACING10' 'RFSPACING11' 'RFSPACING12'
                    'RFSPACING13' 'RFSPACING14' 'RFSPACING15' 'RFOFFSETX'
                    'RFOFFSETY' 'RFRADIUS' 'RFDEPTH' 'RFFREQUENCY'
                    'RFMITERFRACTION' 'RFBENDMODE' 'RFNUMBERLEGS'
                    'RFNUMBERPAIRS' 'RFNUMBERTURNS' 'RFCAPACITANCE'
                    'RFRESISTANCE' 'RFINDUCTANCE' 'RFPADSTACKNAME'
                    'RFPADSSMNAME1' 'RFPADSSMNAME2' 'RFPADBEGINLAYER'
                    'RFPADENDLAYER' 'RFPADLINEWIDTH1' 'RFPADLINEWIDTH2'
                    'RFPADDIAMETER1' 'RFPADDIAMETER2' 'RFPADLENGTH1'
                    'RFPADLENGTH2' 'RFHOLEDIAMETER' 'RFPADANGLE' 'RFDRANAME'
                    'RFPADTYPE' 'RFUID' 'RFBLOCK' 'RFDCNET'
    SUPPRESS_GLOBAL_SHORT_CHECK OFF
    DEBUG    0
    DEFAULT_PHYS_DES_PREFIX U
    FEEDBACK 'OFF'
    INCLUDE_PPT u:/cadence_libs/released/part_table
    MAX_ERRORS 999
    NET_NAME_CHARS   @ - ! # % & ( ) * . / : ? [ ] ^ _ ` +
                     = > 0 1 2 3 4 5 6 7 8 9
    NET_NAME_LENGTH 31
    NUM_OLD_VERSIONS 3
    OPTIMIZE OFF
    REUSE_REFDES ON
    OPF_OPTIMIZATION OFF
    HARD_LOC_SEC OFF
    FORCE_PTF_ENTRY OFF
    REGENERATE_PHYSICAL_NET_NAME OFF
    SCH_POWER_GROUP_WINS_OVER_PPT OFF
    NULL_OPT_VALID OFF
    USE_VECTOR_NOTATION ON
    FILTER_ECS_FROM_XNET ON
    OUTPUT 'ON'
    PACKAGE_PROP 'GROUP' 'ROOM'
    PART_TYPE_LENGTH 128
    PPT u:/cadence_libs/released/part_table
    REF_DES_LENGTH 31
    REPACKAGE ON
    ELECTRICAL_CONSTRAINTS ON
    OVERWRITE_CONSTRAINTS ON
    RUN_DIR ./worklib/design_ce_eu_power_board/packaged/
    STRICT_PACKAGE_PROP 'REUSE_INSTANCE'
    USE_LIBRARY_PPT ON
    USE_STATE OFF
    WARNINGS ON
    LIBRARY 'ce_eu_power_board_lib' 'standard' 'ant' 'battery' 'capacitor_bp'
             'capacitor_pol' 'coil_inductor' 'connector' 'diode' 'diode_zener'
             'display_lcd' 'display_led' 'ferrite_bead' 'filter' 'fuse' 'ic'
             'jumper_wire' 'misc' 'radio' 'res' 'res_network' 'sensor' 'switch'
             'thermistor' 'transformer' 'transistor' 'unreleased' 'varistor'
             'vreg' 'xtal_osc'
    CDSPROP_FILE
    VIEW_PTF part_table
    VIEW_PACKAGER packaged
    VIEW_CONSTRAINTS constraints
    DESIGN_LIBRARY ce_eu_power_board_lib
    DESIGN_NAME design_ce_eu_power_board
    VIEW_CONFIG_PHYSICAL cfg_package
    SD_SUFFIX_SEPARATOR _
    STOP_PST_GEN_ON_PTF_MISMATCH ON
    IGNORE_PRIM_BINDING OFF
    LOG_INST_PHYS_PATH ON
    ANNOTATE_VISIBLE_SEC OFF
    PTF_MISMATCH_EXCLUDE_INJ_PROP 'ALL'
    IMPORT_HFS_HARDSEC_ON_SWAP_PINS OFF
    ALLOW_PTFVALUE_INITIAL_BLANKS ON
    PRESERVE_UNSUBSTITUTED_MACROS OFF
    CACHE_ENABLED OFF
    CACHE_NAME cache
    PTF_NAME cache

**************************************************************
* End processing project file and command line (00:00:00) *
**************************************************************

Creating Configuration "cfg_package" for Design "design_ce_eu_power_board"

Processing Constraints File ./worklib/design_ce_eu_power_board/constraints/des~
ign_ce_eu_power_board.dcf.
INFO(SPCODD-181): Loading c:\cadence\SPB_16.2\share\cdssetup\cdsprop.tmf.
INFO(SPCODD-181): Loading c:\cadence\SPB_16.2\share\cdssetup\cdsprop.paf.
#1   WARNING(SPCODD-360): PPT file "u:/cadence_libs/released/part_table" not ~
found in any of the directories specified by the PPT directive.

*********************************
* Loading the design database *
*********************************

#1   ERROR(SPCODD-103): Could not find logical part '1A' for primitive instan~
ce '@CE_EU_POWER_BOARD_LIB.DESIGN_CE_EU_POWER_BOARD(SCH_1):PAGE1_I8@DIODE.DIO_~
SCHOTTKY(CHIPS)'.
Check 'PART_NAME' property in chips_prt file.
INFO(SPCOPK-1441): 1 errors detected
INFO(SPCOPK-1443): 1 warnings detected
INFO(SPCOPK-1448): Use Tools->Markers->Packager in ConceptHDL to highlight ins~
tances for the errors/warnings reported.
    Start time   11:25:43
    End time     11:25:47
    Elapsed time 0:00:04

**************************************************
* FATAL ERROR PackagerXL exiting with status 2 *
**************************************************
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