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Shape parameters - thermal/anti - pos layer

stump1019

When editing Dynamic Shape Instance Parameters what are the factors that come into play with regard to controlling the copper web between pins if you make your Thru pin, SMD pin and Via settings to Thermal/anti ? This is on a positive layer shape.

 

 

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  • stump1019

    Maybe I was a little too vague with my request.......I was assuming that all of the above was already taken into consideration. What happened is that I had a 25 pin registration coupon having the same pitch between pins but varying anti pad sizes throughout the array. When doing the anti pad to anti pad calculations I was expecting a certain size web, when what was happening is that it became oversized totally blowing the web away. So I guess what I'm really asking is when using the thermal/anti pad what constraints (aka shape to pad/via) would affect this to make it oversized? I would think that if you choose thermal/anti pad that's what you'd get with on other constraints affecting it.

     

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  • stump1019

    Maybe I was a little too vague with my request.......I was assuming that all of the above was already taken into consideration. What happened is that I had a 25 pin registration coupon having the same pitch between pins but varying anti pad sizes throughout the array. When doing the anti pad to anti pad calculations I was expecting a certain size web, when what was happening is that it became oversized totally blowing the web away. So I guess what I'm really asking is when using the thermal/anti pad what constraints (aka shape to pad/via) would affect this to make it oversized? I would think that if you choose thermal/anti pad that's what you'd get with on other constraints affecting it.

     

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