Nets are not enabled during, component placement?

Hi,

Why you see the cross-like Rats nets it because these nets have a VOLTAGE property on them. They are defined as Power or Ground nets.

That also why you cannot see them in CM under electrical. But if you look in Physical/Spacing/Same Net Spacing or Properties you will see these nets.

So it looks right if these nets are Power/Ground!

Regards,

Johan Javinder

Yeah  you was correct Johan.Some components are connected to the voltage line. In case i want to put routing for that components means it is possible.

Then i had updated  the netlist again and again, but the nets are not enabled on the component.

I want to complete board urgently. Any possible tricks to enable the nets for routing.

Hi,

You should be able to route these as is!

The square with the cross are the Rats Nets for nets with power. So you can route them as any other net if you want. Or drop a via thru the board and place a power plane on a layer to connect them all.

//Johan

Johan thank  you for your reply.  But your concept will worth only of multilayer board, Me was considering with the working on two layer board. In case the the component was in the top means i will put the track on bottom side with thru via.

Can you tell solution for working on double layer board. Me had tried to update the netlist, not succeeded. Mainly the voltage nets are get affected during the updation .

Then i had highlighted the warning occured. The voltage is 24V  & G1 (Ground).The net rev warning occurred  during the netlist updation.

The warning netrev file is below.

(---------------------------------------------------------------------)

(                                                                     )

(   Allegro Netrev Import Logic                                     )

(                                                                     )

(   Drawing         : dsn7.brd                                     )

(   Software Version : 16.6S038                                     )

(   Date/Time       : Mon Dec 01 11:44:28 2014                     )

(                                                                     )

(---------------------------------------------------------------------) 

------ Directives ------------

Ripup etch:                 No

Ripup delete first segment: No

Ripup retain bondwire:       No

Ripup symbols:               Never

Missing symbol has error:   No

DRC update:                 Yes

Schematic directory:         'D:\PCB EDITOR\DESIGN 7\allegro'

Design Directory:           'D:/PCB Editor/Design 7'

Old design name:             'D:/PCB Editor/Design 7/test7.brd'

New design name:             'D:/PCB Editor/Design 7/test7.brd'

CmdLine: netrev.exe -y 3 -i D:\PCB EDITOR\DESIGN 7\allegro D:\PCB Editor\Design 7\test7.brd D:\PCB Editor\Design 7\test7.brd

------ Preparing to read pst files ------

Starting to read D:/PCB EDITOR/DESIGN 7/allegro/pstchip.dat

Finished reading D:/PCB EDITOR/DESIGN 7/allegro/pstchip.dat (00:00:00.05)

Starting to read D:/PCB EDITOR/DESIGN 7/allegro/pstxprt.dat

   Finished reading D:/PCB EDITOR/DESIGN 7/allegro/pstxprt.dat (00:00:00.00)

Starting to read D:/PCB EDITOR/DESIGN 7/allegro/pstxnet.dat

   Finished reading D:/PCB EDITOR/DESIGN 7/allegro/pstxnet.dat (00:00:00.01) 

------ Oversights/Warnings/Errors ------ 

#1   WARNING(SPMHNI-316): Property warning detected.

WARNING(SPMHNI-217): Problems with net 'G1'. Error with net property 'VOLTAGE' and value 'GND': 'Incorrect syntax'. 

------ Library Paths ------

MODULEPATH = .

           C:/Cadence/SPB_16.6/share/local/pcb/modules

PSMPATH = .

           symbols           ..

           ../symbols

           C:/Cadence/SPB_16.6/share/local/pcb/symbols

           C:/Cadence/SPB_16.6/share/pcb/pcb_lib/symbols

           C:/Cadence/SPB_16.6/share/pcb/allegrolib/symbols

PADPATH = .

           symbols           ..

           ../symbols

           C:/Cadence/SPB_16.6/share/local/pcb/padstacks

           C:/Cadence/SPB_16.6/share/pcb/pcb_lib/symbols

           C:/Cadence/SPB_16.6/share/pcb/allegrolib/symbols 

------ Summary Statistics ------ 

netrev run on Dec 1 11:44:28 2014

   DESIGN NAME : 'TEST 7'

   PACKAGING ON Oct 15 2014 05:53:32

   COMPILE 'logic'

   CHECK_PIN_NAMES OFF

   CROSS_REFERENCE OFF

   FEEDBACK OFF

   INCREMENTAL OFF

   INTERFACE_TYPE PHYSICAL

   MAX_ERRORS 500

   MERGE_MINIMUM 5

   NET_NAME_CHARS '#%&()*+-./:=>?@[]^_`|'

   NET_NAME_LENGTH 24

   OVERSIGHTS ON

   REPLACE_CHECK OFF

   SINGLE_NODE_NETS ON

   SPLIT_MINIMUM 0

   SUPPRESS   20

   WARNINGS ON

No error detected

No oversight detected

1 warnings detected 

cpu time     0:00:43

elapsed time 0:00:00