Stats

  • Locked Locked
  • Replies 7
  • Subscribers 166
  • Views 7777
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

"Thru Pin to Thru Via Spacing" Error?

Hossein1357

Hi,

I read somewhere that using spacer holes like below is a wise way.

I am trying to put some via around the pad of my spacer footprint. However, I receive DRC errors (Thru Pin to Thru Via Spacing) when I place some via on my big pad

How can I create a symbol like above picture?

Thanks,

Hossein

Parents
  • Hossein1357

    Thank you Steve very much for your help. The document is also very good. However, after updating my PCB with the modified symbol I still see same net spacing errors for shape and via.

    I am using Same Net rules. Shall I remove this rule in order to get rid of these errors? Or, I need to do some work around.

    Thanks,

    Hossein

Reply
  • Hossein1357

    Thank you Steve very much for your help. The document is also very good. However, after updating my PCB with the modified symbol I still see same net spacing errors for shape and via.

    I am using Same Net rules. Shall I remove this rule in order to get rid of these errors? Or, I need to do some work around.

    Thanks,

    Hossein

Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.