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"Thru Pin to Thru Via Spacing" Error?

Hossein1357

Hi,

I read somewhere that using spacer holes like below is a wise way.

I am trying to put some via around the pad of my spacer footprint. However, I receive DRC errors (Thru Pin to Thru Via Spacing) when I place some via on my big pad

How can I create a symbol like above picture?

Thanks,

Hossein

  • steve
    In the symbol this is fine. The symbol has no net awareness so you will see DRC's. When you place the symbol in a design the vias take on the same net as the pin and your pin to pin DRC's will not be there UNLESS you activate the same net DRC's. The following link is something similar http://www.parallel-systems.co.uk/images/PDF/Mechanical_Via_Arrays.pdf
  • Hossein1357

    Thank you Steve very much for your help. The document is also very good. However, after updating my PCB with the modified symbol I still see same net spacing errors for shape and via.

    I am using Same Net rules. Shall I remove this rule in order to get rid of these errors? Or, I need to do some work around.

    Thanks,

    Hossein

  • steve
    Yes - either turn of the same net DRC or waive the DRC
  • Hossein1357

    I see that two modified holes have islands after applying changes and waiving DRCs!. However, I don't see these messages for the rest of holes?!

  • Hossein1357
    It's a long time since I posted my problem and seems there is no response to it. i need urgent help. Thanks all
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