Unable to open .sch file in Orcad Lite 16.6.

I have a .sch file generated from Questa Prime (Mentor).

I am trying to open it  with ORCAD so that I can edit the same. However, when I follow the below steps all I get is a text file describing signal names, color, orientation etc. with no errors.

How can i view the symbol file in ORCAD? Kindly provide suggestions

Sample of text file is shown below:

WindowType IncrementalSchematic
DesignChecksum e7ZGO96?4RMXzCKPOfV3?0
RoutedNets {}
RoutedInst {}
WindowPreferences {showhierarchy 1 showacttime 1 inoutlocation 1 selequivnets 0 hidebuffers 0 hidecells 1 hideinverters 0 selectenv 1 autowave 1 lognets 1 popupenabled 1 mouseoverenabled 1 showdunames 0 showinstnames 1 shownetnames 0 shownetnamestyle corner shownetstate 0 showpinnames 1 showripindices 1 showvalues 1 verticaltext 1 netxFollowsControlLogic 0 netxMaxGates 1024 netxMaxLevels 32 use_code_preview 1 time0_warning 1 depth_warning 1 add_error_warning 1 diverge_warning 1}
EndOfStateInfo
# File saved with Nlview version 6.4.4_0 (04/08/25-18:45:38 bk=1.779)
#
property -reset
property autobundle 20
property boxcolor0 #00ffff
property boxcolor1 #999999
property boxinstcolor #ffffff
property boxpincolor #00ffff
property buscolor #ffff00
property closeenough 3
property enablebufferchaincollapsing 1
property enablescrollrect 1
property evaluateattrvalue 1
property extractsequentiallogic 2
property gatepinname 1
property inferbundlename 1
property instattrmax 50
property objecthighlight3 #00ff00
property objecthighlight4 #ff00ff
property objecthighlight5 #ffd700
property objecthighlight6 #0000ff
property objecthighlight9 #fa8072
property outboxcolor1 #a52a2a
property outboxcolor2 #000000
property outboxcolor4 #000000
property picksubnet 1
property pinattrmax 50
property pinorder 2
property recursivecallerrorlen 10
property searchvisibleobjects 1
property selectbycolor9 1
property showcellname 0
property showmarks 1
property shownetattr 4
property showripindex 3
property timelimit 50

module new v {} -nosplit
load symbol work.BUF_RCTL(fast) v HIERGEN portBus BUF_RCTL_SINF output.right 68 {BUF_RCTL_SINF[0]} {BUF_RCTL_SINF[1]} {BUF_RCTL_SINF[2]} {BUF_RCTL_SINF[3]} {BUF_RCTL_SINF[4]} {BUF_RCTL_SINF[5]} {BUF_RCTL_SINF[6]} {BUF_RCTL_SINF[7]} {BUF_RCTL_SINF[8]} {BUF_RCTL_SINF[9]} {BUF_RCTL_SINF[10]} {BUF_RCTL_SINF[11]} {BUF_RCTL_SINF[12]} {BUF_RCTL_SINF[13]} {BUF_RCTL_SINF[14]} {BUF_RCTL_SINF[15]} {BUF_RCTL_SINF[16]} {BUF_RCTL_SINF[17]} {BUF_RCTL_SINF[18]} {BUF_RCTL_SINF[19]} {BUF_RCTL_SINF[20]} {BUF_RCTL_SINF[21]} {BUF_RCTL_SINF[22]} {BUF_RCTL_SINF[23]} {BUF_RCTL_SINF[24]} {BUF_RCTL_SINF[25]} {BUF_RCTL_SINF[26]} {BUF_RCTL_SINF[27]} {BUF_RCTL_SINF[28]} {BUF_RCTL_SINF[29]} {BUF_RCTL_SINF[30]} {BUF_RCTL_SINF[31]} {BUF_RCTL_SINF[32]} {BUF_RCTL_SINF[33]} {BUF_RCTL_SINF[34]} {BUF_RCTL_SINF[35]} {BUF_RCTL_SINF[36]} {BUF_RCTL_SINF[37]} {BUF_RCTL_SINF[38]} {BUF_RCTL_SINF[39]} {BUF_RCTL_SINF[40]} {BUF_RCTL_SINF[41]} {BUF_RCTL_SINF[42]} {BUF_RCTL_SINF[43]} {BUF_RCTL_SINF[44]} {BUF_RCTL_SINF[45]} {BUF_RCTL_SINF[46]} {BUF_RCTL_SINF

Thanks,

Ansh