• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design
  3. Rat shown on via despite connection

Stats

  • Locked Locked
  • Replies 7
  • Subscribers 166
  • Views 16488
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Rat shown on via despite connection

Bijanbina
Bijanbina over 7 years ago

In Allegro 17.2 HF045 when I add shape or cline to connect a pin to pin still the rats for some via is shown. As in picture below clearly both pin are connected but the rat is shown. How can I fix this? This happen in many part of the board.

If anything more is needed like via padstack or a test board please let me know

  • Cancel
Parents
  • excellon1
    excellon1 over 7 years ago

    Hi

    Maybe try this. In the picture you have two overlapping shapes that are associated with the net "AV1B_SW" near the bottom left hand side of the chip. Merge these shapes so they don"t overlap. To do that go to shapes > merge shapes on the tool bar. click one of the shapes then click the other. They should merge into one shape.

    Next re-route the cline that is connecting to that AV1B_SW shape plane from the pin at the bottom right hand side of the chip.

    See if the nets go away. The other thing to check is that your vias associated with the A1VB_SW net are truly connected to a plane or trace on the other layers of the board. They may not be !

    Paul.

    • Cancel
    • Vote Up +1 Vote Down
    • Cancel
  • Bijanbina
    Bijanbina over 7 years ago in reply to excellon1

    Thanks Paul for your reply.

    I tried use merge on two shape but the second shape is actually an exposed pin defined in symbol (I cant select it in merge command). I removed the power plane and take a new screenshot. What is clear to me is that the the parts are connected on Top layer (colored as red). Nevertheless allegro show rats. Isn't a single connection point sufficient? Should it have connection from internal alternative layer too?

    Also I removed vias but the rats remained (between two shape and chip A1V8_SW pin)

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • steve
    steve over 7 years ago in reply to Bijanbina

    The issue is that the shape and cline does not connect to the origin of the Pin. You MUST make sure that any clines or shapes cover the origin point of the pin to make connection,

    • Cancel
    • Vote Up +1 Vote Down
    • Cancel
  • Bijanbina
    Bijanbina over 7 years ago in reply to steve

    Thanks steve. problem solved. BTW are you the man behind parsys youtube channel? I watch those and really love them. I couldn't be here without those videos.

    • Cancel
    • Vote Up +1 Vote Down
    • Cancel
  • stumpsr1019
    stumpsr1019 over 7 years ago in reply to Bijanbina

    Believe that might be a gentleman named Gary Hinde, and I agree that they are fantastic.

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
  • steve
    steve over 7 years ago in reply to stumpsr1019

    Not Gary but Steve :-) and thanks for the feedback guys. Keep watching there will be some new ones soon....

    • Cancel
    • Vote Up +1 Vote Down
    • Cancel
  • Bijanbina
    Bijanbina over 7 years ago in reply to steve

    WOW! I just want you to know that you are a true gentleman. Thanks Steve for your great videos. Hope you the best

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Bijanbina
    Bijanbina over 7 years ago in reply to steve

    WOW! I just want you to know that you are a true gentleman. Thanks Steve for your great videos. Hope you the best

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information