Concept HDL Error

Hi Al,

There can be a couple causes for this error. I found this Solution posted on SourceLink. For search criteria, I
entered "ERROR 304 : Cannot find a .sir file for". Please see this SourceLink URL - http://sourcelink.cadence.com/docs/db/kdb/2004/June/11140772.html

Here's the content of the Solution# 11140772:
*Error_Message:


#1 ERROR(304): Cannot find a .sir file for '@test_lib.abc(sch_1)'. Ve~
rify you have saved all changes to cell 'capacitor'.
In addition, verify the correct library for cell 'abc' has been ~
specified in the liblist of all cfg_package/expand.cfg files used during expan~
sion of this design.

*Problem:


I am trying to run Export physical on my design and I am getting the Error 304. How
do I resolve this error?

*Solution:


This reason why this error occurs is because the entity view of the component for
which this error is being reported does not have the vlog004u.sir file. In order
to generate the files for the components in question, please follow these steps:

a) Locate all the components (one-by-one) reported by this Error #304 by viewing
the pxl.log file by selecting any particular instance for that component in the
schematic.
b) In ConceptHDL, double-click on that component instance to view the symbol.
c) Now do a File->Save in ConceptHDL in order to save the symbol. This will
regenerate the entity view and will generate the vlog004u.sir file as well.
d) Repeat the steps a - c for all the other components in error.
e) Save the design and re-run Export Physical.

Jerry

Hi Jerry,

It worked actually. Thanks! Now I have a new problem. I need to generate the footprint of the schematic symbol. I got my symbol from http://www.accelerated-designs.com. It is a PQ208 Package of Xilinx FPGA XC3S200. It has a CSV file (.ctx file extension). The guy from ADI says i need a footprint generator to generate the footprint. You know of any Allegro product which does this?

Thanks,

Al

Hi Jerry,

It worked actually. Thanks! Now I have a new problem. I need to generate the footprint of the schematic symbol. I got my symbol from http://www.accelerated-designs.com. It is a PQ208 Package of Xilinx FPGA XC3S200. It has a CSV file (.ctx file extension). The guy from ADI says i need a footprint generator to generate the footprint. You know of any Allegro product which does this?

Thanks,

Al

Hi Jerry,

It worked actually. Thanks! Now I have a new problem. I need to generate the footprint of the schematic symbol. I got my symbol from http://www.accelerated-designs.com. It is a PQ208 Package of Xilinx FPGA XC3S200. It has a CSV file (.ctx file extension). The guy from ADI says i need a footprint generator to generate the footprint. You know of any Allegro product which does this?

Thanks,

Al

Hi Al,

Glad the solution above resolved your problem. I'm a front-end (ConceptHDL/PCB Librarian/etc.) type person and don't have much experience with footprint/pad
building.

From what you've described, you have a .CSV file. While this Excel format can be
imported into PCB Librarian to generate the schematic symbol and chips.prt
files, I don't know of a method to automatically generate the footprint from
a .CSV file. Of course, you would use Allegro PCB Editor to build the padstacks
and footprint - but this is a manual process - easy, but manual.

You may try posting another message with the subject line of how to automatically
generate an Allegro footprint from a Xilinx .CSV file.

Good luck,

Jerry