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Concept HDL Error

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Hi guys! Al here again. I encountered an error while saving my schematic entry. The error reads Place holder property needs value set.

And when I am exporting the physical definition I encounter this error:

#1 ERROR(304): Cannot find a .sir file for '@pcb_lib.xc3s200pq208(entity)'. ~

Verify you have saved all changes to cell 'xc3s200pq208'.

In addition, verify the correct library for cell 'xc3s200pq208' has be~

en specified in the liblist of all cfg_package/expand.cfg files used during ex~

pansion of this design.

When binding to '@pcb_lib.xc3s200pq208(chips)', the port definition is~

determined using the 'entity' view.

1 errors detected

Thanks for the help. Ü

- Al


Originally posted in cdnusers.org by acbalbason
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    Hi Jerry,

    It worked actually. Thanks! Now I have a new problem. I need to generate the footprint of the schematic symbol. I got my symbol from http://www.accelerated-designs.com. It is a PQ208 Package of Xilinx FPGA XC3S200. It has a CSV file (.ctx file extension). The guy from ADI says i need a footprint generator to generate the footprint. You know of any Allegro product which does this?

    Thanks,

    Al


    Originally posted in cdnusers.org by acbalbason
Reply
  • archive

    Hi Jerry,

    It worked actually. Thanks! Now I have a new problem. I need to generate the footprint of the schematic symbol. I got my symbol from http://www.accelerated-designs.com. It is a PQ208 Package of Xilinx FPGA XC3S200. It has a CSV file (.ctx file extension). The guy from ADI says i need a footprint generator to generate the footprint. You know of any Allegro product which does this?

    Thanks,

    Al


    Originally posted in cdnusers.org by acbalbason
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