Stats

  • Locked Locked
  • Replies 5
  • Subscribers 164
  • Views 2967
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

TestPrep Automatic- Allow pin escape insertion problem

archive

Hi guys

Has any you used the Allow pin escape insertion feature on the Automatic TestPrep ?
i understand that this feature adds via (as ICT ) so it needs to check/move all traces in all layers where it wants to add a via.

I have a board of about 3300 nets and want to add ICT's to (only 2700 need ICT).
when running the the TestPrep with the Allow pin escape insertion  feature checked then the ICT insertion rate is very slow
and when i say slow i mean 63 nets proccessed in  11 hours (over night)
i have a strong PC with XP Prof with 1G of Ram and Allegro Preformance

when i run the same just without this feature then it finishes after about 1 hour ( with 3 passes - eg. 3 probe types enabled) (results are 1300 ICT added out of 2700 nets need ICT)

Has any of you used this feature ? with any success ?
am i doing something wrong ? or did i forget to do something ?

attached the testprep automatic form and general parameters TAB with checked features

thank you for the help
roby


Originally posted in cdnusers.org by robyd
Parents
  • archive

    Roby,

    I have not seen this in the past but it has been a while since I asked TestPrep to add in a large amount of missing test points using the "auto insertion" feature.

    I have a couple tips for you that may help you figure out what is going on.

    1. Test Prep does not allows add test points if it creates a DRC. It something does not do a good job bubbling traces away from a newly added test point which can cause addition failures because it creating DRCs. I would recommend you check "Disable cline bubbling" in the Testprep Parameters form and see if you can get more test points in using via replacement. In most cases you can easily clean up the DRC that are left behind after the test point is added.

    2. Dynamic shapes appears to prevent the addition of test points using the "auto insertion" feature so I would remove them prior to running the auto insertion pass and see if you get a higher completion rate. Of course generate a Sub-Drawing of them to be added back in later.

    3. Hilite the nets that are missing test points and see if you could find a test point location that appears to be a good test site. Try to add a test point manually to an existing via and if it fails review the error echoed on the command line to investigate it further.

    Overall, during the fanout of the design I attempt to space the vias out is such a way so they can be used as test points so I never run into the situation that you have that no test point sites are available.

    Hope this helps,
    Mike Catrambone
    UTStarcom, Inc.


    Originally posted in cdnusers.org by mcatramb91
Reply
  • archive

    Roby,

    I have not seen this in the past but it has been a while since I asked TestPrep to add in a large amount of missing test points using the "auto insertion" feature.

    I have a couple tips for you that may help you figure out what is going on.

    1. Test Prep does not allows add test points if it creates a DRC. It something does not do a good job bubbling traces away from a newly added test point which can cause addition failures because it creating DRCs. I would recommend you check "Disable cline bubbling" in the Testprep Parameters form and see if you can get more test points in using via replacement. In most cases you can easily clean up the DRC that are left behind after the test point is added.

    2. Dynamic shapes appears to prevent the addition of test points using the "auto insertion" feature so I would remove them prior to running the auto insertion pass and see if you get a higher completion rate. Of course generate a Sub-Drawing of them to be added back in later.

    3. Hilite the nets that are missing test points and see if you could find a test point location that appears to be a good test site. Try to add a test point manually to an existing via and if it fails review the error echoed on the command line to investigate it further.

    Overall, during the fanout of the design I attempt to space the vias out is such a way so they can be used as test points so I never run into the situation that you have that no test point sites are available.

    Hope this helps,
    Mike Catrambone
    UTStarcom, Inc.


    Originally posted in cdnusers.org by mcatramb91
Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.