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TestPrep Automatic- Allow pin escape insertion problem

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Hi guys

Has any you used the Allow pin escape insertion feature on the Automatic TestPrep ?
i understand that this feature adds via (as ICT ) so it needs to check/move all traces in all layers where it wants to add a via.

I have a board of about 3300 nets and want to add ICT's to (only 2700 need ICT).
when running the the TestPrep with the Allow pin escape insertion  feature checked then the ICT insertion rate is very slow
and when i say slow i mean 63 nets proccessed in  11 hours (over night)
i have a strong PC with XP Prof with 1G of Ram and Allegro Preformance

when i run the same just without this feature then it finishes after about 1 hour ( with 3 passes - eg. 3 probe types enabled) (results are 1300 ICT added out of 2700 nets need ICT)

Has any of you used this feature ? with any success ?
am i doing something wrong ? or did i forget to do something ?

attached the testprep automatic form and general parameters TAB with checked features

thank you for the help
roby


Originally posted in cdnusers.org by robyd
Parents
  • archive

    Hi Mike

    thank you for the info

    but my main question was about the rate of  automatic testprep works
    i now deleted all shapes in the design an rerun it
    aftre 4 hours of work it processed 12 nets out of 3263 ( see picture attached )
    and it is still running ......


    i also run it with out the allow pin escape and it runs fast enough ( about 1.5 hours with 3 diff probes)

    another question i have about the manual ICT
    it only adds ICT (SMT) on via or trace or pad
    but if i want to add near an existing via / pad/trace ( and then connect to it ) it is not possible
    so i put it on a pad with DRC and move it and after that route to it ( very complicated !)
    is there a better way to add ICT on adense board ?

    same problem when i want to add ict over a trace in the middle of the net
    how can i do it ?
    i first added avia manualy then tried to replace it to ICT with no succes
    so i added a small trace out of this via ( on bottom ) and i was able to add on the line/trace a smt ICT - when tried to move the SMT ICT over the VIA got a DRC

    again is there a better way to insert a TH via ICT on a trace running on internal layer ?

    thank you

    roby Drath
    MEMTEK Elec Eng


    Originally posted in cdnusers.org by robyd
Reply
  • archive

    Hi Mike

    thank you for the info

    but my main question was about the rate of  automatic testprep works
    i now deleted all shapes in the design an rerun it
    aftre 4 hours of work it processed 12 nets out of 3263 ( see picture attached )
    and it is still running ......


    i also run it with out the allow pin escape and it runs fast enough ( about 1.5 hours with 3 diff probes)

    another question i have about the manual ICT
    it only adds ICT (SMT) on via or trace or pad
    but if i want to add near an existing via / pad/trace ( and then connect to it ) it is not possible
    so i put it on a pad with DRC and move it and after that route to it ( very complicated !)
    is there a better way to add ICT on adense board ?

    same problem when i want to add ict over a trace in the middle of the net
    how can i do it ?
    i first added avia manualy then tried to replace it to ICT with no succes
    so i added a small trace out of this via ( on bottom ) and i was able to add on the line/trace a smt ICT - when tried to move the SMT ICT over the VIA got a DRC

    again is there a better way to insert a TH via ICT on a trace running on internal layer ?

    thank you

    roby Drath
    MEMTEK Elec Eng


    Originally posted in cdnusers.org by robyd
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