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  3. TestPrep Automatic- Allow pin escape insertion problem

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TestPrep Automatic- Allow pin escape insertion problem

archive
archive over 18 years ago

Hi guys

Has any you used the Allow pin escape insertion feature on the Automatic TestPrep ?
i understand that this feature adds via (as ICT ) so it needs to check/move all traces in all layers where it wants to add a via.

I have a board of about 3300 nets and want to add ICT's to (only 2700 need ICT).
when running the the TestPrep with the Allow pin escape insertion  feature checked then the ICT insertion rate is very slow
and when i say slow i mean 63 nets proccessed in  11 hours (over night)
i have a strong PC with XP Prof with 1G of Ram and Allegro Preformance

when i run the same just without this feature then it finishes after about 1 hour ( with 3 passes - eg. 3 probe types enabled) (results are 1300 ICT added out of 2700 nets need ICT)

Has any of you used this feature ? with any success ?
am i doing something wrong ? or did i forget to do something ?

attached the testprep automatic form and general parameters TAB with checked features

thank you for the help
roby


Originally posted in cdnusers.org by robyd
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  • archive
    archive over 18 years ago

    Roby,

    I sort of didn't answer your initial question. It is hard to tell what exactly is going on..
    It is running the old allegro no-via router router to insert the additional test sites.
    Sometimes the old router would run very very slow when you had your routing grid set too fine so I did a little test board and found out that this is still the case.

    My Test board ran for 10 minutes and was made up of the following:
    - 1 inch sq PCB
    - 10 nets
    - 6 components
    - Routing grid set to 1 mil

    What is your Routing Grid set to ? This sounds like the reason why it is running so long.

    Your question: "Manual ICT only adds ICT (SMT) on via or trace or pad but is it possible to add it near an existing via/ pad/trace"
    I believe what you are looking for is to stub off of a existing via/pad/trace. What I have done in the past is setup my TestPrep Parameters and develop a small script to stub off a feature then add a test point which I alias to a function key. Here is a small example:

    # Add test point stub script
    # Enter add connect command and select trace
    # to be tested prior to running this script

    setwindow pcb
    ipick 0 -100
    next
    testprep manual
    ipick 0 0
    done
    add connect

    # End of Add test point stub script

    Of course you will need to tweak the script a little to work for you.

    Your question: " first added a via manually then tried to replace it to ICT with no success"
    You need to define a Thru Via under the Padstack Selection tab and also check the Replace Vias box at the bottom for it to work correctly.

    Your question: "I want to add ict over a trace in the middle of the net" "better way to insert a TH via ICT on a trace running on internal layer"
    As long as you define a SMT TestPad Padstack under the Padstack Selection tab you should be able to add a test point in the middle of a trace. Note: This only works for traces on the external layers because it uses a surface pad not a Thru hole test point.

    Hope this helps,
    Mike Catrambone
    UTStarcom, Inc.


    Originally posted in cdnusers.org by mcatramb91
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  • archive
    archive over 18 years ago

    Roby,

    I sort of didn't answer your initial question. It is hard to tell what exactly is going on..
    It is running the old allegro no-via router router to insert the additional test sites.
    Sometimes the old router would run very very slow when you had your routing grid set too fine so I did a little test board and found out that this is still the case.

    My Test board ran for 10 minutes and was made up of the following:
    - 1 inch sq PCB
    - 10 nets
    - 6 components
    - Routing grid set to 1 mil

    What is your Routing Grid set to ? This sounds like the reason why it is running so long.

    Your question: "Manual ICT only adds ICT (SMT) on via or trace or pad but is it possible to add it near an existing via/ pad/trace"
    I believe what you are looking for is to stub off of a existing via/pad/trace. What I have done in the past is setup my TestPrep Parameters and develop a small script to stub off a feature then add a test point which I alias to a function key. Here is a small example:

    # Add test point stub script
    # Enter add connect command and select trace
    # to be tested prior to running this script

    setwindow pcb
    ipick 0 -100
    next
    testprep manual
    ipick 0 0
    done
    add connect

    # End of Add test point stub script

    Of course you will need to tweak the script a little to work for you.

    Your question: " first added a via manually then tried to replace it to ICT with no success"
    You need to define a Thru Via under the Padstack Selection tab and also check the Replace Vias box at the bottom for it to work correctly.

    Your question: "I want to add ict over a trace in the middle of the net" "better way to insert a TH via ICT on a trace running on internal layer"
    As long as you define a SMT TestPad Padstack under the Padstack Selection tab you should be able to add a test point in the middle of a trace. Note: This only works for traces on the external layers because it uses a surface pad not a Thru hole test point.

    Hope this helps,
    Mike Catrambone
    UTStarcom, Inc.


    Originally posted in cdnusers.org by mcatramb91
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