TestPrep Automatic- Allow pin escape insertion problem

Hi Mike

thank you for the effort and the share of your idea's

now i understand that a "OLD" router is involved i understand
i see that there is a log being generated tprouter.log ( which i don't understand at all)
but i found that it includs a time column which was in average 4-5 minutes i assume per try/via
any way my board is about 110 Sq in and the grid was 5 mils.
i changed it to 50 mils and rerun it
now in ran about 5 min BUT... only 3 ICT inserted !! (2-3 seconds per try in the tprouter.log)
tried with grid of 25 mils and it ran 14 minutes with 5 ICT !?!(7-10 seconds per try in the tprouter.log)
another try with 10 mil grid (which is still running)  i get about 1 minute per row in the log file

it seems that when the allow insertion is enabled that the regular via replacement or smt over trace (on bottom) is disabled - it is not logical !

when i ran it with 5 mil grid with out the allow pin insertion checked so only pad stack replacement and smt ICT added on tarces was done there were 1300 ICT inserted in less then 30 minutes ( in a faster machine )

when i understood that grid may cause the algorithm not to find possible ICT locations that also satisfy the grid i decided to lower it to 0.1 mil and run it without the allow pin insertion and see if i get a higher ICT count ( more then 1300)
the result was the same i think i got the exact ICT count
so my theory is not right !

any way i understand that the preofrmance of the automatic pin insertion feature is less then POOR ! or else you can suggest any thing else?
it is not working as expected.

about the idea of script ( and alias) it is very good
but it lacks in that the length and direction of the stub are different for each and every case.
so i my idea is : (did not try it yet)
after adding the stub as desired ( direction and length)
to excute ( by funckey x "done;setwindow pcb;testprep manual;ipick 0 0;done;add connect"

done ( of the previous add connect)
setwindow pcb
testprep manual
ipick 0 0
done
add connect

and then continue add stub to the next place
do you thing it will work ?

about the replace regular via to ICT one i probably did something wrong.since i have it defined in the replacment table TAB and it is enabled

about my last question
i meant that i want to add an ICT in amiddle of  a trace that runs in internal layer!
so i want to be able ( theoretically ) to add a TH ICT VIA on the middle of an internal trace.and to benefit from the good push and shove feature of the allegro.
so now after your tip about the script i guess i can change to fit this case also
or else you have a better solution ?

again thank you very much for your effort.
Roby Drath
MEMTEK Elec Eng

Hi Mike

thank you for the effort and the share of your idea's

now i understand that a "OLD" router is involved i understand
i see that there is a log being generated tprouter.log ( which i don't understand at all)
but i found that it includs a time column which was in average 4-5 minutes i assume per try/via
any way my board is about 110 Sq in and the grid was 5 mils.
i changed it to 50 mils and rerun it
now in ran about 5 min BUT... only 3 ICT inserted !! (2-3 seconds per try in the tprouter.log)
tried with grid of 25 mils and it ran 14 minutes with 5 ICT !?!(7-10 seconds per try in the tprouter.log)
another try with 10 mil grid (which is still running)  i get about 1 minute per row in the log file

it seems that when the allow insertion is enabled that the regular via replacement or smt over trace (on bottom) is disabled - it is not logical !

when i ran it with 5 mil grid with out the allow pin insertion checked so only pad stack replacement and smt ICT added on tarces was done there were 1300 ICT inserted in less then 30 minutes ( in a faster machine )

when i understood that grid may cause the algorithm not to find possible ICT locations that also satisfy the grid i decided to lower it to 0.1 mil and run it without the allow pin insertion and see if i get a higher ICT count ( more then 1300)
the result was the same i think i got the exact ICT count
so my theory is not right !

any way i understand that the preofrmance of the automatic pin insertion feature is less then POOR ! or else you can suggest any thing else?
it is not working as expected.

about the idea of script ( and alias) it is very good
but it lacks in that the length and direction of the stub are different for each and every case.
so i my idea is : (did not try it yet)
after adding the stub as desired ( direction and length)
to excute ( by funckey x "done;setwindow pcb;testprep manual;ipick 0 0;done;add connect"

done ( of the previous add connect)
setwindow pcb
testprep manual
ipick 0 0
done
add connect

and then continue add stub to the next place
do you thing it will work ?

about the replace regular via to ICT one i probably did something wrong.since i have it defined in the replacment table TAB and it is enabled

about my last question
i meant that i want to add an ICT in amiddle of  a trace that runs in internal layer!
so i want to be able ( theoretically ) to add a TH ICT VIA on the middle of an internal trace.and to benefit from the good push and shove feature of the allegro.
so now after your tip about the script i guess i can change to fit this case also
or else you have a better solution ?

again thank you very much for your effort.
Roby Drath
MEMTEK Elec Eng