Stats

  • Locked Locked
  • Replies 5
  • Subscribers 164
  • Views 2969
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

TestPrep Automatic- Allow pin escape insertion problem

archive

Hi guys

Has any you used the Allow pin escape insertion feature on the Automatic TestPrep ?
i understand that this feature adds via (as ICT ) so it needs to check/move all traces in all layers where it wants to add a via.

I have a board of about 3300 nets and want to add ICT's to (only 2700 need ICT).
when running the the TestPrep with the Allow pin escape insertion  feature checked then the ICT insertion rate is very slow
and when i say slow i mean 63 nets proccessed in  11 hours (over night)
i have a strong PC with XP Prof with 1G of Ram and Allegro Preformance

when i run the same just without this feature then it finishes after about 1 hour ( with 3 passes - eg. 3 probe types enabled) (results are 1300 ICT added out of 2700 nets need ICT)

Has any of you used this feature ? with any success ?
am i doing something wrong ? or did i forget to do something ?

attached the testprep automatic form and general parameters TAB with checked features

thank you for the help
roby


Originally posted in cdnusers.org by robyd
Parents
  • archive

    Hi Mike
    one more thing i just found
    i decreased my max via displacement from 300 mil to 50 mil
    and tha process is faster but still relative slow to the try without the allow insertion

    max 300 mil displacement with 5 mil grid gives 3600 possible via sites to be checked
    while
    max 50 mil displacement with 10 mil grid gives 25 valid ICT sites to be checked !

    it still does not explain why when i ran it with 50 mil grid  ( and other 2 feature checked beside allow insertion)
    it only added 3 ICT's ?
    from one point of view you want small grid so more via's can be replaced
    form the other hand you want higher grid to reduce run time
    what is the optimum ?

    or maybe it should be run in 2 stages
    small grid without insertion
    and then ( in incremental mode ) higher grid with allow insertion

    what do you think ?

    so now i run it (with 2 stages ) and see after few hours what is the progress

    Roby Drath
    MEMTEK Elec Eng


    Originally posted in cdnusers.org by robyd
Reply
  • archive

    Hi Mike
    one more thing i just found
    i decreased my max via displacement from 300 mil to 50 mil
    and tha process is faster but still relative slow to the try without the allow insertion

    max 300 mil displacement with 5 mil grid gives 3600 possible via sites to be checked
    while
    max 50 mil displacement with 10 mil grid gives 25 valid ICT sites to be checked !

    it still does not explain why when i ran it with 50 mil grid  ( and other 2 feature checked beside allow insertion)
    it only added 3 ICT's ?
    from one point of view you want small grid so more via's can be replaced
    form the other hand you want higher grid to reduce run time
    what is the optimum ?

    or maybe it should be run in 2 stages
    small grid without insertion
    and then ( in incremental mode ) higher grid with allow insertion

    what do you think ?

    so now i run it (with 2 stages ) and see after few hours what is the progress

    Roby Drath
    MEMTEK Elec Eng


    Originally posted in cdnusers.org by robyd
Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.