Stats

  • Locked Locked
  • Replies 2
  • Subscribers 164
  • Views 12730
  • Members are here 0
More Content
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to setup design rules for one chip?

archive

Allegro version is 15.7.

One chip(U1, mcu) 's design rule is different from the rest circuit,
now i want to setup a design rule for U1(pin to pin : 10mil),
how to setup it in constraints menu.
the more detailed, the better.

thanks in advance.


Originally posted in cdnusers.org by watchdog1976
Parents Reply Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.