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How to route High-speed SDRAM

I will layout one PCB that contains one ARM soc(AT91SAM9261) & one SDRAM(MT48LC16M16A2).
SDARM will connect with ARM soc.

from SDRAM's datasheet, its max clock frequecy is about 133MHz.

for it is the first time for me to layout high-speed board.

how should i do when placing parts and routing?

how to confirm the address/data/clock trace width/length?

thanks

Originally posted in cdnusers.org by watchdog1976

archive over 17 years ago

You should continue with refering the data sheet of SDRAM. Because in high speed boards, every parts has different features. And the board wants a lots of consideration of placement and routing such as signal integrity and so on. It is with my knowledge. If i'm wrong anyone can correct me.

Thanks,

Originally posted in cdnusers.org by shiva
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archive over 17 years ago

Posted By shiva on 1/18/2008 12:18 AM

You should continue with refering the data sheet of SDRAM. Because in high speed boards, every parts has different features. And the board wants a lots of consideration of placement and routing such as signal integrity and so on. It is with my knowledge. If i'm wrong anyone can correct me.

Thanks,
Thanks for your comments.

I have download SDRAM datasheet from micron website, but in datasheet, there is no any
description about how to layout & palce SDRAM.

Originally posted in cdnusers.org by watchdog1976
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archive over 17 years ago

In my knowledge the SDRAM should be as close as possible to the processor. Here that is AT91SAM9261 microcontroller. And the address/data traces should be length matched. Make sure about high frequency clock signal. You can refer the data sheet of microcontroller. And also see this link:
http://www.idt.com/products/getDoc.cfm?docID=6728316
http://www.cdnusers.org/InterviewDesigninginDDR2memoriesonPCBs/tabid/401/Default.aspx

Thanks.

Originally posted in cdnusers.org by shiva
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archive over 17 years ago

no
for SDRAM, no length-matching is required, its a synchronous system, not a source-syn DDR.
your ARM processor generates the clk for the memory. you have to take it into account when determining the maximum trace length for all the other memory-interface signals.
length matching is coming from timing analysis: http://www.edn.com/article/CA236412.html
my calculator for timing: http://www.buenos.extra.hu/iromanyok/PCB_Timing_analysis.xls

trace width: for 133MHz SDRAM it doesnt have to be Z0 controlled. so make it to be narrow: technology minimum at your fab. separation>dielectric_higth

Originally posted in cdnusers.org by buenos
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archive over 17 years ago

Thanks for your information. It's very useful.

Originally posted in cdnusers.org by shiva
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