• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design

PCB Design

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

PCB Design

Latest Posts

  • Create a new Post
  • Discussion

    How to handle the Via or Thru-Hole plating thickness value?? Is it available?

    Category: PCB Design

    By ichliebedich

    $usertype

    •

    started over 4 years ago

    0 replies • 8844 views
  • Discussion

    allegro package menu file (apd.men) not working

    Category: PCB Design

    By ichliebedich

    $usertype

    •

    updated over 4 years ago by ichliebedich

    1 replies • 9684 views
  • Discussion

    L293DNE Quadruple Half-H Drivers

    Category: PCB Design

    By kaylee

    $usertype

    •

    started over 4 years ago

    0 replies • 9198 views
  • Discussion

    DE HDL Printing Net Attributes

    Category: PCB Design

    By tmd63

    $usertype

    •

    started over 4 years ago

    0 replies • 8902 views
  • Discussion

    Aliases nested too deeply

    Category: PCB Design

    By charliejuk

    $usertype

    •

    started over 4 years ago

    0 replies • 9440 views
  • Discussion

    Copper pull back

    Category: PCB Design

    By HSID

    $usertype

    •

    updated over 4 years ago by excellon1

    1 replies • 10520 views
  • Discussion

    ROHS FPGA in a leaded process

    Category: PCB Design

    By atoddrich

    $usertype

    •

    started over 4 years ago

    0 replies • 8781 views
  • Discussion

    Allegro Free Pysical Viewer 17.2 show measure min. setting

    Category: PCB Design

    By Leapsy Tom

    $usertype

    •

    started over 4 years ago

    0 replies • 10235 views
  • Discussion

    PCB editor snap condition error

    Category: PCB Design

    By cornebos1

    $usertype

    •

    updated over 4 years ago by cornebos1

    1 replies • 9711 views
  • Discussion

    Hierarchal schematic design

    Category: PCB Design

    By FormerMember

    $usertype

    •

    updated over 4 years ago by oldmouldy

    1 replies • 4104 views
  • Discussion

    how to create panel in orcad 17.4 pcb designer professional

    Category: PCB Design

    By keerthankitty

    $usertype

    •

    updated over 4 years ago by AvengerThanos

    1 replies • 10345 views
  • Discussion

    A bus of netgroups

    Category: PCB Design

    By stevensen1

    $usertype

    •

    updated over 4 years ago by AvengerThanos

    1 replies • 10162 views
  • Discussion

    Edit Page name is disabled

    Category: PCB Design

    By Commander5112

    $usertype

    •

    started over 4 years ago

    0 replies • 9910 views
  • Discussion

    OrCAD Capture TCL script to set variant view.

    Category: PCB Design

    By alager

    $usertype

    •

    started over 4 years ago

    0 replies • 9838 views
  • Discussion

    padstack question

    Category: PCB Design

    By masamasa

    $usertype

    •

    updated over 4 years ago by steve

    1 replies • 9305 views
<>
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information