Tips to resolve Convergence

Based on your feedback on our last poll, below are some tips to resolve Convergence error in PSpice

To calculate the bias point, DC sweep and transient analysis for analog devices PSpice must solve a set of nonlinear equations which describes the circuit's behavior.

In a few cases PSpice cannot find a solution to the nonlinear circuit equations and this is called a “convergence problem.”

Common causes Of Convergence failure in Allegro PSpice Simulator are:

• Lack of Limiting
• Rapid Voltage Transitions
• Model Discontinuities
• ABM expression singularities
• Large Floating Capacitors

Enable Auto Convergence options in case tool throws convergence error. You can enable auto convergence from Simulation Settings > Options > Analog Simulation, as shown below:

Above functionality should avoid your most of the convergence problems but below are few troubleshooting guidelines for Convergence Failure:

• Examine the non-convergence error message in the .out file to further localize the problem. In the previous/current iteration voltage printout, note the largest voltages (as large as 1E10) to help find the root the problem.
• Check the direction of independent and dependent current sources. A convergence problem can result when current is forced backward through diodes or p-n junctions.
• Check that diodes are forward biased in the reported voltages for the last iteration. Add a shunt resistor if necessary to keep them forward biased.
• Look for large currents for the problem devices and currents. A current or voltage that reaches +/-1E10 indicates that the maximum value has been reached. These locations are often the starting point of nonconvergence. For high power circuits where currents exceed 1000A, it will be necessary to increase ABSTOL, as the default (1e-12) is set for IC currents.
• Check if IC=0 is set for all the capacitors in design. This is needed to change the initial state of the circuit to make it suitable for bias point convergence.
• If a particular model is a suspect, isolate it in a test circuit to attempt to generate similar DC curves. If a single device shows the problem, look for unrealistic model parameters. Try simplifying the model to obtain better convergence.
• Divide the circuit into smaller pieces and simulate them individually.
• Check for singularities in ABM expressions. Look for denominators which contain circuit variables. Try adding a small offset to the denominator to prevent it from becoming zero.
• Make sure that all the circuit connections are valid. Check for incorrect node numbering or dangling nodes. Also, verify component polarity.
• Check for syntax mistakes. Make sure that you used the correct PSPICE units (i.e., MEG for 1E6, not M, which means milli in simulations).
• Make sure that voltage/current generators use realistic values and verify that the syntax is correct.
• Make sure that dependent source gains are correct, and that E/G element expressions are reasonable. Verify that division by zero or LOG (0) cannot occur.
• Make sure that there are no unrealistic model parameters; especially if you have manually entered the model into the netlist.
• Avoid using digital components, unless necessary. Initialize the nodes with valid digital value to ensure the state is not ambiguous.

Once you have verified the circuit using above points and still getting convergence error, then check PSpice options for the type of convergence error as below

• BIAS POINT (DC) Convergence
  • Increase ITL1 to 400 from Simulation Settings > Options > Analog Simulation > General
  • Enable STEPGMIN from Simulation Setting > Options > Analog Advanced > Bias Point
  • Enable PREORDER from Simulation Settings > Options > Analog Simulation > General
    
    
• DC SWEEP Convergence
  • Increase ITL2 to 100 from Simulation Settings > Options > Analog Simulation > General
  • Increase or decrease the step values, which are used in the. DC sweep
  • Try running the transient simulation with Parametric sweep option to sweep DC source
    
    
• TRANSIENT Convergence
  • Set RELTOL=.01 from Simulation Settings > Options > Analog Simulation > General
  • Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it. Do it from Simulation Settings > Options > Analog Simulation > General
  • Increase ITL4, but to no more than 100
  • Try using SKIPBP option from Simulation Settings > Analysis > Time Domain > General Settings

Team DesignTech

Cadence Design Systems