• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      oldmouldy
      oldmouldy 55 Points
    • 2
      steve
      steve 25 Points
    • 3
      Robert Finley
      Robert Finley 20 Points
    • 3
      JCTEYSSIER0
      JCTEYSSIER0 20 Points
    • 5
      excellon1
      excellon1 15 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,848 Points
    • 2
      oldmouldy
      oldmouldy 11,055 Points
    • 3
      eDave
      eDave 7,631 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,226 Points
    • 5
      redwire
      redwire 5,188 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Discussion

    Outline for drill chart has disappeared.

    Category: PCB Design

    By archive

    •

    updated over 17 years ago by archive

    4 replies • 13751 views
  • Discussion

    Allegro Editor Shut Off

    Category: PCB Design

    By archive

    •

    updated over 17 years ago by archive

    1 replies • 12884 views
  • Discussion

    using component footprint in allegro 15.7 for 15.2

    Category: PCB Design

    By archive

    •

    updated over 17 years ago by archive

    1 replies • 12989 views
  • Discussion

    CIS hidden symbol power pins causes strange Allegro behavior

    Category: PCB Design

    By archive

    •

    updated over 17 years ago by archive

    5 replies • 15483 views
  • Discussion

    Q: embedding a binary in a SKILL procedure

    Category: Allegro X PCB Editor

    By archive

    •

    updated over 17 years ago by archive

    2 replies • 13440 views
  • Discussion

    How we can convert the Font of the text in board under silkscreen or etch class .

    Category: PCB Design

    By archive

    •

    started over 17 years ago

    0 replies • 12896 views
  • Discussion

    Translating Orcad netlist to Allegro

    Category: PCB Design

    By archive

    •

    updated over 17 years ago by archive

    4 replies • 15212 views
  • Discussion

    Gerber Generation Errors

    Category: PCB Design

    By archive

    •

    updated over 17 years ago by archive

    3 replies • 14398 views
  • Discussion

    A Question Regarding Properties fixed within Board Partitioning

    Category: PCB Design

    By archive

    •

    updated over 17 years ago by archive

    2 replies • 13741 views
  • Discussion

    online DRC with bond channel outline

    Category: PCB Design

    By archive

    •

    started over 17 years ago

    0 replies • 12846 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information