• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      oldmouldy
      oldmouldy 55 Points
    • 2
      excellon1
      excellon1 35 Points
    • 3
      steve
      steve 25 Points
    • 4
      Ejlersen
      Ejlersen 20 Points
    • 4
      Robert Finley
      Robert Finley 20 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,863 Points
    • 2
      oldmouldy
      oldmouldy 11,055 Points
    • 3
      eDave
      eDave 7,641 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,226 Points
    • 5
      redwire
      redwire 5,193 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Discussion

    Can i create a capture schematic by pspice netlist

    Category: PCB Design

    By zfan

    •

    started over 7 years ago

    0 replies • 12868 views
  • Discussion

    3D Canvas Export

    Category: PCB Design

    By Emmett

    •

    updated over 7 years ago by Emmett

    2 replies • 13896 views
  • Discussion

    Schematic <--> Layout Synchronization

    Category: PCB Design

    By AitneInc

    •

    updated over 7 years ago by Lancia1

    4 replies • 6380 views
  • Discussion

    How to simulate a fully differential input/output buffer .ibis model in Cadence Virtuoso?!

    Category: Allegro X APD

    By bitan1990

    •

    started over 7 years ago

    0 replies • 1543 views
  • Discussion

    Create Netlist renames nets instead of changing reference designators.

    Category: PCB Design

    By Lennie

    •

    started over 7 years ago

    0 replies • 13086 views
  • Discussion

    Doube symbol

    Category: PCB Design

    By Filo88

    •

    updated over 7 years ago by Filo88

    6 replies • 14715 views
  • Discussion

    Thermal Pad Spoke Angle

    Category: PCB Design

    By Emmett

    •

    updated over 7 years ago by Emmett

    2 replies • 13941 views
  • Discussion

    importing Ultra Library file to create footprint

    Category: Allegro X PCB Editor

    By WongWingJoshua

    •

    started over 7 years ago

    0 replies • 13502 views
  • Discussion

    How to create Homogeneous packages in Allegro Concept HDL

    Category: PCB Design

    By chadga

    •

    started over 7 years ago

    0 replies • 12966 views
  • Discussion

    Creating Context skill in SPB17.2

    Category: Allegro X PCB Editor

    By seyerfred

    •

    updated over 7 years ago by Chise

    4 replies • 14217 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information