• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      avant
      avant 55 Points
    • 1
      KS202606109251
      KS202606109251 55 Points
    • 3
      BC202603263145
      BC202603263145 26 Points
    • 4
      JV202605125312
      JV202605125312 20 Points
    • 4
      JR202606119023
      JR202606119023 20 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,598 Points
    • 2
      oldmouldy
      oldmouldy 10,805 Points
    • 3
      eDave
      eDave 7,391 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,231 Points
    • 5
      redwire
      redwire 4,458 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Discussion

    ORCIS-6085 Could Not read part information

    Category: PCB Design

    By cyclops116

    •

    updated over 12 years ago by cyclops116

    4 replies • 22902 views
  • Discussion

    PSPICE V16.5 sensitive to UAC setting

    Category: PCB Design

    By rhodesengr

    •

    updated over 12 years ago by rhodesengr

    1 replies • 14292 views
  • Discussion

    Text to Hole Constraint

    Category: PCB Design

    By jjhappyland

    •

    updated over 12 years ago by esemper1

    2 replies • 14166 views
  • Discussion

    Through via on trace does not generate DRC error.

    Category: PCB Design

    By esemper1

    •

    updated over 12 years ago by steve

    5 replies • 15056 views
  • Discussion

    Alias for arrow keys.

    Category: PCB Design

    By Lennie

    •

    updated over 12 years ago by Lennie

    4 replies • 15274 views
  • Discussion

    Route Keep In

    Category: PCB Design

    By Yoda5939

    •

    updated over 12 years ago by steve

    1 replies • 14699 views
  • Discussion

    CREF error

    Category: PCB Design

    By rwetz

    •

    updated over 12 years ago by Jerry GenPart

    2 replies • 17892 views
  • Discussion

    XML Parser

    Category: Allegro X PCB Editor

    By archive

    •

    updated over 12 years ago by Ejlersen

    9 replies • 19061 views
  • Discussion

    Suppressing product related warnings

    Category: PCB Design

    By Pawandeep

    •

    updated over 12 years ago by Pawandeep

    2 replies • 17215 views
  • Discussion

    OrCAD 16.5 Extracting Gerber files.

    Category: PCB Design

    By Elixz

    •

    updated over 12 years ago by ScottCad

    6 replies • 19311 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information