• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. PCB Design & IC Packaging (Allegro X)

PCB Design & IC Packaging (Allegro X)

CDNS Forum PCB Categories

Allegro X PCB Editor

Allegro X Capture CIS

Allegro X System Capture (EE Cockpit)

Allegro X Pulse & EDM

Allegro X APD

Allegro X Scripting - Skill

Allegro X Scripting - TCL

PCB Design Archive

Design Entry HDL

PSpice

Licensing & Installation

  • Leaderboard

    PCB Design

    • 1
      steve
      steve 20 Points
    • 1
      Ejlersen
      Ejlersen 20 Points
    • 1
      excellon1
      excellon1 20 Points
    • 4
      HirokiJEM
      HirokiJEM 16 Points
    • 5
      Robert Finley
      Robert Finley 15 Points
  • Leaderboard

    PCB Design

    • 1
      steve
      steve 15,898 Points
    • 2
      oldmouldy
      oldmouldy 11,035 Points
    • 3
      eDave
      eDave 7,651 Points
    • 4
      DavidJHutchins
      DavidJHutchins 5,226 Points
    • 5
      redwire
      redwire 5,193 Points

Feedback, Suggestions, and Questions

Provide feedback on the forums or any other part of the site. Questions and suggestions welcome.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Forum - Thread List

Latest Posts

  • Suggested Answer

    How to add APD 15.5 cns_space_values.form at 17.4

    Category: Allegro X Scripting - Skill

    By FormerMember

    •

    updated over 1 year ago by Xiaome8

    4 replies • 1920 views
  • Answered

    via to via spacing on the same layer

    Category: Allegro X PCB Editor

    By masamasa

    •

    updated over 1 year ago by Hoangkhoipcb

    7 replies • 6405 views
  • Suggested Answer

    shape to void conversion

    Category: Allegro X PCB Editor

    By masamasa

    •

    updated over 1 year ago by Hoangkhoipcb

    6 replies • 5812 views
  • Not Answered

    Need help extracting net alias names

    Category: Allegro X Capture CIS

    By AB_1717543042707

    •

    updated over 1 year ago by AB_1717543042707

    2 replies • 2956 views
  • Not Answered

    How to set amplifier model tolerance?

    Category: PSpice

    By Zhengzhi Wang

    •

    updated over 1 year ago by TechiEE12

    3 replies • 3483 views
  • Answered

    Plotting to PDF in Design Entry HDL

    Category: Design Entry HDL

    By dd2661

    •

    updated over 1 year ago by jc teyssier

    10 replies • 10016 views
  • Not Answered

    Syscap power object name don't change

    Category: Allegro X System Capture (EE Cockpit)

    By xmlee

    •

    updated over 1 year ago by rg13

    1 replies • 1436 views
  • Not Answered

    Orcad X on ARM architecture

    Category: Licensing and Installation

    By vicvicvarunis

    •

    updated over 1 year ago by rg13

    1 replies • 2659 views
  • Discussion

    SysCap – Tip of the Week: How to save table of contents (TOC) in schematic design automatically

    Category: Allegro X System Capture (EE Cockpit)

    By DesignTech

    •

    started over 1 year ago

    0 replies • 3048 views
  • Suggested Answer

    Ghost NETCLASS property on nets in PCB editor - cannot be found anywhere in constraints manager

    Category: Allegro X PCB Editor

    By AleksMK

    •

    updated over 1 year ago by John T

    4 replies • 2443 views
<>

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information